SPR154
Abstract: MPC509 ef80 FC-24
Text: Freescale Semiconductor, Inc. MOTOROLA Order this document by MPC509TS/D SEMICONDUCTOR TECHNICAL DATA MPC509 Technical Summary Freescale Semiconductor, Inc. PowerPC MPC509 RISC Microcontroller The MPC509 is a member of the PowerPC Family of reduced instruction set computer RISC microcontrollers (MCUs). The MPC509 implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types
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MPC509TS/D
MPC509
MPC509
32-bit
SPR154
ef80
FC-24
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LPC24XX
Abstract: timer video tms 9937 LPC2478FBD208 mst 702 lf LPC2468 pcb LPC2478 ARM7TDMI motor driver ic 7324 LPC247x LPC2478 pcb LPC2468FBD208
Text: UM10237 LPC24XX User manual Rev. 04 — 26 August 2009 User manual Document information Info Content Keywords LPC2400, LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, LPC2478, ARM, ARM7, 32-bit, Single-chip, External memory interface, USB 2.0, Device, Host, OTG, Ethernet, CAN, I2S, I2C, SPI, UART, PWM, IRC,
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UM10237
LPC24XX
LPC2400,
LPC2458,
LPC2420,
LPC2460,
LPC2468,
LPC2470,
LPC2478,
32-bit,
timer video tms 9937
LPC2478FBD208
mst 702 lf
LPC2468 pcb
LPC2478 ARM7TDMI
motor driver ic 7324
LPC247x
LPC2478 pcb
LPC2468FBD208
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Untitled
Abstract: No abstract text available
Text: MPC5567_REVB MPC5567BCE Rev. APR2013 2013 Rev. 3030APR Freescale Semiconductor Mask Set Errata Mask Set Errata for Mask REVB Introduction This report applies to mask REVB for these products: • MPC5567 ID before 15 MAY 2008 ID from 15 May 2008 to 30 JUNE
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MPC5567
MPC5567BCE
APR2013
MPC5567
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Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor Mask Set Errata MPC5565_REVA MPC5565ACE Rev. APR2013 2013 Rev. 3030 APR Mask Set Errata for Mask REVA Introduction This report applies to mask REVA for these products: • MPC5565 ID before 15 MAY 2008 ID from 15 May 2008 to 30 JUNE
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MPC5565
MPC5565ACE
MPC5565
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ADSP-21000
Abstract: ADSP-21020 ADSP-21060 ADSP-21062 ADSP-21062L tddg
Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21062L SUMMARY High Performance Signal Processor for Communications, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O
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ADSP-2106x
ADSP-21062/ADSP-21062L
32-Bit
240-Lead
225-Ball
40-Bit
ADSP-21062KS-133
ADSP-21062KS-160
ADSP-21000
ADSP-21020
ADSP-21060
ADSP-21062
ADSP-21062L
tddg
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MAX232 G4
Abstract: IC404 IC808 ic401 diode C728 diode c729 transistor C721 IC818 ic811 C729
Text: MPC555 Evaluation Board Schematics A B C D VCC3_3 1 2 3 4 5 6 7 8 9 10 R101 4K75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC5 VCC3_3 CLKOUT B_CNTX0 B_CNRX0 1 6 2 7 3 8 4 9 5 TP102 TP103 CB100 100n /SRESET /PORESET A_CNTX0 A_CNRX0 TP100 TP101 SUBD9
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MPC555
TP102
TP103
CB100
TP100
TP101
CO101
MAX232-6
MAX232-2
MAX232-13
MAX232 G4
IC404
IC808
ic401
diode C728
diode c729
transistor C721
IC818
ic811
C729
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sandisk eMMC 4.41
Abstract: toshiba emmc 4.4 spec SANDISK inand Samsung eMMC 4.41 sandisk emmc 4.5 bcm 4330 programming Guide Sandisk iNAND eMMC toshiba emmc 4.4 linux toshiba emmc 4.4.1 spec sandisk inand extreme emmc
Text: An addendum for this document is available. See Document ID#: IMX25RMAD. i.MX25 Multimedia Applications Processor Reference Manual Supports i.MX251 MCIMX251 i.MX253 (MCIMX253) i.MX255 (MCIMX255) i.MX257 (MCIMX257) i.MX258 (MCIMX258) IMX25RM Rev. 1 06/2009
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IMX25RMAD.
MX251
MCIMX251)
MX253
MCIMX253)
MX255
MCIMX255)
MX257
MCIMX257)
MX258
sandisk eMMC 4.41
toshiba emmc 4.4 spec
SANDISK inand
Samsung eMMC 4.41
sandisk emmc 4.5
bcm 4330 programming Guide
Sandisk iNAND eMMC
toshiba emmc 4.4 linux
toshiba emmc 4.4.1 spec
sandisk inand extreme emmc
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GSM intercom circuit diagram
Abstract: sharc ADSP-21xxx architecture sharc ADSP-21xxx general block diagram sharc 21xxx architecture block diagram sharc ADSP-21xxx ADSST-DAP-EVAL01 fingerprint scanner circuit ADSP-21060 1994 MIP FLOAT LEVEL SWITCH NAT 40 reliance electric 20 hp DC motor drives
Text: 35 DSP Selection Guide 2001 Edition 19:30:35 18:30:35 12:30:35 11:30:35 09:30:35 02:30:35 01:30:35 23:00:35 19:30 Table of Contents Introduction to ADI DSPs 16-Bit DSP Key Products 32-Bit DSP Key Products ADI DSP Overview Markets & Applications Key Benefits
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16-Bit
32-Bit
ADSP-2100
ADSP-21000
AD73xxx
GSM intercom circuit diagram
sharc ADSP-21xxx architecture
sharc ADSP-21xxx general block diagram
sharc 21xxx architecture block diagram
sharc ADSP-21xxx
ADSST-DAP-EVAL01
fingerprint scanner circuit
ADSP-21060 1994
MIP FLOAT LEVEL SWITCH NAT 40
reliance electric 20 hp DC motor drives
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an1171
Abstract: sharc ADSP-21xxx ADDRESSING MODES CHN 950 ADSP-21062 ADSP21535 ADSP-21535 ADSP-2188M ADSP-2191 ADSP-TS101S DSM2150F5V
Text: DSM2150F5V DSM Digital Signal Processor System Memory For Analog Devices DSPs (3.3V Supply) FEATURES SUMMARY • Glueless Connection to DSP – Create state machines, chip selects, simple shifters and counters, clock dividers, delays – Easily add memory, logic, and I/O to the External Port of ADSP-218x, 219x, 2106x,
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DSM2150F5V
ADSP-218x,
2106x,
2116x,
2153x,
TS101
16-bit
an1171
sharc ADSP-21xxx ADDRESSING MODES
CHN 950
ADSP-21062
ADSP21535
ADSP-21535
ADSP-2188M
ADSP-2191
ADSP-TS101S
DSM2150F5V
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Untitled
Abstract: No abstract text available
Text: SIU SYSTEM INTERFACE UNIT REFERENCE MANUAL PREFACE This manual defines the functionality of the system interface unit SIU and peripherals control unit (PCU). The SIU and PCU are modules in the Motorola MPC500 family of microcontrollers (MCUs). MPC500 family microcontrollers contain an SIU,
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MPC500
MPC500
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ADSP-21160 reference manual
Abstract: ADSP-21160 EC Bus
Text: ;7(51$/0(025< Figure 8-0. Listing 8-0. Table 8-0. 2YHUYLHZ ([WHUQDO0HPRU\,QWHUIDFH The ADSP-21160 external memory interface has several enhancements over that of the ADSP-2106x. These changes were introduced to improve bus throughput when interfacing to synchronous memories and
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ADSP-21160
ADSP-2106x.
32-bit
48-bit
64-bit
ADSP-21160 reference manual
EC Bus
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CAN BUS
Abstract: ADSP-21160 virpt ADSP-21060
Text: 08/7,352& 66,1* Table 10-0. Figure 10-0. Listing 10-0. 2YHUYLHZ The ADSP-21160 includes functionality and features that allow the design of multiprocessing DSP systems. These features include distributed, on-chip arbitration for the shared external bus; a unified
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ADSP-21160
ADSP-21160s
75HJLVWHU6WDWXV
ADSP-21160)
CAN BUS
virpt
ADSP-21060
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super harvard architecture block diagram
Abstract: addressing modes of dsp processors 21000 DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER sharc ADSP-2106x architecture ADSP-21060 register file block diagram of speech recognition how dsp is used in radar working and block diagram of ups dsp 32 c processor fast page mode dram controller
Text: Introduction 1.1 1 OVERVIEW The ADSP-2106x SHARC—Super Harvard Architecture Computer—is a high-performance 32-bit digital signal processor for speech, sound, graphics, and imaging applications. The SHARC builds on the ADSP-21000 Family DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip
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ADSP-2106x
32-bit
ADSP-21000
ADSP-2106x.
ADSP-21060/62
ADSP-21061
super harvard architecture block diagram
addressing modes of dsp processors 21000
DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER
sharc ADSP-2106x architecture
ADSP-21060 register file
block diagram of speech recognition
how dsp is used in radar
working and block diagram of ups
dsp 32 c processor
fast page mode dram controller
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Untitled
Abstract: No abstract text available
Text: a Commercial Grade SHARC Family DSP Microcomputer ADSP-21061/ADSP-21061L SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Architecture Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O
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ADSP-21061/ADSP-21061L
32-bit
240-Lead
225-Ball
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SuperSPARC
Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys
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STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
STP1020HS
STP1091
SuperSPARC
Mbus master 250 slave circuit
tmx390
STP1091-60
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Z32100
Abstract: z32104
Text: Zilog P r o du c t S p e c i f i c a t i o n J a n u a ry 1987 /oc€>o4 Z32104 D M A C O N TR O LL ER D ESCRIPTIO N T h e Z32104 D M A C o n tro lle r D M A C is a m em ory-m apped p e rip h e ra l device th a t p erfo rm s m em ory-to-m em ory, m em ory-to-peripheral, and
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Z32104
Z32100
32-bit
133-pin
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a00u
Abstract: Z32100 STK 411 230 WE32100 ALI m7 101b BUX 707 z32101 Z32103 BUDA lo4p
Text: Y " P ro d u ct S pecification January 1987 Z32103 D R A M C O N TR O LLER DESCRIPTION T he Z32103 D R A M Controller provides address multiplexing, access and cycle time management, and refresh control for dynam ic random access m emory DRAM . It provides, in a single chip,
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Z32103
32-bit
a00u
Z32100
STK 411 230
WE32100
ALI m7 101b
BUX 707
z32101
BUDA
lo4p
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WE32100
Abstract: ALI m7 101b WE32104
Text: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a mem ory-mapped peripheral device that performs memory-to-memory, memory fill, mem ory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that
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32-bit
133-pin
225pF)
WE32100
ALI m7 101b
WE32104
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Untitled
Abstract: No abstract text available
Text: ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21060 ANALOG DEVICES SUMMARY High Performance Signal Processor for Communica tions, Graphics, and Imaging Applications Super Harvard ARchitecture Computer SHARC — Four Independent Buses for Dual Data Fetch,
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ADSP-2106x
ADSP-21062/ADSP-21060
32-Bit
ADSP-21060KS-133*
ADSP-21060KS-160*
ADSP-21060LKS-133*
ADSP-21060LKS-160*
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Untitled
Abstract: No abstract text available
Text: ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP-21060C/ADSP-21060LC ANALOG DEVICES SU M M A R Y High Performance Signal Processor for Com munica tions, Graphics, and Im aging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch,
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ADSP-21060
ADSP-21060C/ADSP-21060LC
32-Bit
ADSP-21060CZ-133
ADSP-21060CZ-160
ADSP-21060CW-133
ADSP-21060CW-160
ADSP-21060LCW
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Untitled
Abstract: No abstract text available
Text: ADSP-2106X SHARC DSP Microcomputer Family ANALOG DEVICES ADSP-21061/ADSP-21061L S UM M AR Y High Performance Signal Com puter for Speech, Sound, Graphics and Imaging Applications Super Harvard Architecture Com puter SHARC — Four Independent Buses for Dual Data, Instructions,
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ADSP-2106X
ADSP-21061/ADSP-21061L
32-Bit
SP-21061
240-lead
-21061L
225-Ball
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zct02
Abstract: SZ1 AMI
Text: P r e l im in a r y P r o d u c t S p e c if ic a t io n V % Z80185/Z80195 S m a r t P e r ip h e r a l C o n t r o l l e r s FEATURES • 0°C to +70°C Temperature Range ■ Enhanced Z8S180 MPU ■ Four Z80 CTC Channels 100-Pin QFP Package ■ One Channel ESCC” Controller
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Z80185/Z80195
Z80185
Z80195
512KB
Z8S180
100-Pin
Z80195
parall5/Z80195
zct02
SZ1 AMI
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Untitled
Abstract: No abstract text available
Text: ADSP-2106X SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L ANALOG DEVICES SU M M A R Y High Performance Signal Processor for Com munica tions, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch,
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32-Bit
ADSP-21060KS-133
ADSP-21060KS-160
ADSP-21060LKS-133
ADSP-21060LKS-160
240-lead,
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RY 227 Tf 227 10A
Abstract: SD oid 3C
Text: ADSP- 2106x SHARCF DSP Microcomputer Family ANALOG DEVICES ÆSP-21061/Æ SP-21061L S UM M AR Y High-Performance Signal Com puter for Speech, Sound, Graphics and Imaging Applications Super Harvard Architecture Com puter SHARC — Four Independent Buses for Dual Data, Instructions,
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32-Bit
RY 227 Tf 227 10A
SD oid 3C
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