83c chipset
Abstract: No abstract text available
Text: Contents Section 1 2 3 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SE370C758B
Abstract: P04D SE370C756A TMS370C756A SE370C758A
Text: TMS370Cx5x 8-BIT MICROCONTROLLER SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997 D D D D D D D D D FN / FZ PACKAGE TOP VIEW VSS1 C2 C1 MC C0 B7 B6 B5 B4 B3 B2 B1 B0 D0 / CSE2 / OCF VCC2 VSS2 VCC1 CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume
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TMS370Cx5x
SPNS010F
SE370C758B
P04D
SE370C756A
TMS370C756A
SE370C758A
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SPR154
Abstract: MPC509 ef80 FC-24
Text: Freescale Semiconductor, Inc. MOTOROLA Order this document by MPC509TS/D SEMICONDUCTOR TECHNICAL DATA MPC509 Technical Summary Freescale Semiconductor, Inc. PowerPC MPC509 RISC Microcontroller The MPC509 is a member of the PowerPC Family of reduced instruction set computer RISC microcontrollers (MCUs). The MPC509 implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types
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MPC509TS/D
MPC509
MPC509
32-bit
SPR154
ef80
FC-24
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ADSP-21489 user manual
Abstract: ADSP-21487 sharc ADSP-214xx FFT Accelerator medialb ADSP-21160 ADSP-21161 ADSP-21489 ADSP21487 sharc iir filter IBIS Model diode
Text: SHARC Processor SUMMARY The ADSP-2148x processors are available with unique audiocentric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input
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SP-21486/ADSP-21487/ADSP-21488/ADSP-21489
ADSP-2148x
32-bit/40-bit
D09018-0-12/10
ADSP-21489 user manual
ADSP-21487
sharc ADSP-214xx FFT Accelerator
medialb
ADSP-21160
ADSP-21161
ADSP-21489
ADSP21487
sharc iir filter
IBIS Model diode
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DDR2-667
Abstract: SSTUA32864 SSTUA32866 SSTUA32S865 TFBGA160
Text: SSTUA32S865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications Rev. 02 — 16 March 2007 Product data sheet 1. General description The SSTUA32S865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four 2R x 4 and similar high-density Double Data Rate 2 (DDR2) memory
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SSTUA32S865
28-bit
DDR2-667
SSTUA32S865
14-bit
DDR2-667
SSTUA32864
SSTUA32866
TFBGA160
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ande RY 192
Abstract: ande RY 228 ande RY 227 mov rdn 240 DB14-000121-00
Text: LSI402Z Digital Signal Processor User’s Guide May 2000 Order Number R14014 LSI Logic Confidential This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties
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LSI402Z
R14014
DB15-000131-02,
ande RY 192
ande RY 228
ande RY 227
mov rdn 240
DB14-000121-00
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radix-8 FFT
Abstract: DBGA KD 472 M mov CMAC A15B2 sc sf 12A H4 17ER CI23 honeywell hx3000 HX3000
Text: DSP Architectures RHDSP24 Radiation Hardened Scalable DSP Chip Transform Your WorldTM Data Sheet Real 24 PORT A Imag 24 RHDSP24 Imag 24 24 24 X INPU TB US Y INPUT BU S O U TP U TB US 24 48 Imag 24 Scheduler/ Controller X Y Memory A 24 Memory B 24 System Controls
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RHDSP24
RHDSP24-Y-75-M
DSPA-RHDSP24DS
radix-8 FFT
DBGA
KD 472 M mov
CMAC
A15B2
sc sf 12A H4
17ER
CI23
honeywell hx3000
HX3000
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Untitled
Abstract: No abstract text available
Text: MC9S12XDP512 Data Sheet HCS12X Microcontrollers MC9S12XDP512 Rev. 2.10 5/2005 freescale.com MC9S12XDP512 Data Sheet covers MC9S12XDT384 & MC9S12XA512 MC9S12XDP512V2 Rev. 2.10 5/2005 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
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MC9S12XDP512
HCS12X
MC9S12XDP512
MC9S12XDT384
MC9S12XA512
MC9S12XDP512V2
MC9S12XDP512V1
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Untitled
Abstract: No abstract text available
Text: MC9S12XDP512 Data Sheet HCS12X Microcontrollers MC9S12XDP512 Rev. 2.09 5/2005 freescale.com MC9S12XDP512 Data Sheet covers MC9S12XDT384 & MC9S12XA512 MC9S12XDP512V2 Rev. 2.09 5/2005 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
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MC9S12XDP512
HCS12X
MC9S12XDP512
MC9S12XDT384
MC9S12XA512
MC9S12XDP512V2
MC9S12XDP512V1
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Untitled
Abstract: No abstract text available
Text: Freescale Semiconductor, Inc. DOCUMENT NUMBER MC9S12KG128 Freescale Semiconductor, Inc. MC9S12KG128 SoC Guide V01.01 Original Release Date: 16 JUL 2002 Revised: 08 MAR 2002 Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design.
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MC9S12KG128
112-pin
MC9S12KG128
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LSI403LP
Abstract: No abstract text available
Text: Preliminary – Content Subject to Change LSI403LP Digital Signal Processor Preliminary Datasheet The LSI403LP is a 16-bit, fixed-point digital signal processor DSP based on the ZSP 400 DSP core. The LSI403LP contains an entire DSP system on a single chip, and is designed for applications requiring lower
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LSI403LP
16-bit,
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Untitled
Abstract: No abstract text available
Text: FUJITSU SEMICONDUCTOR CM44-10134-1E CONTROLLER MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90945 Series HARDWARE MANUAL F2MC-16LX 16-BIT MICROCONTROLLER MB90945 Series HARDWARE MANUAL FUJITSU LIMITED PREFACE • Objectives and intended reader Thank you very much for your continued patronage of Fujitsu semiconductor products.
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CM44-10134-1E
2MC-16LX
16-BIT
MB90945
F2MC-16LX
F2MC-16LX
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Untitled
Abstract: No abstract text available
Text: FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM44-10103-5E 2 F MC-16LX 16-BIT MICROCONTROLLER MB90550A/B Series HARDWARE MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90550A/B Series HARDWARE MANUAL Be sure to refer to the “Check Sheet” for the latest cautions on development.
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CM44-10103-5E
2MC-16LX
16-BIT
MB90550A/B
MC-16LX
F2MC-16LX
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Untitled
Abstract: No abstract text available
Text: DOCUMENT NUMBER 9S12H256BDGV1/D MC9S12H256 Device User Guide V01.16 Original Release Date: 29 SEP 2000 Revised: 05 NOV 2003 Motorola, Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
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9S12H256BDGV1/D
MC9S12H256
144-pin
MC9S12H256
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Untitled
Abstract: No abstract text available
Text: FUJITSU SEMICONDUCTOR CM44-10102-5E CONTROLLER MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90570/A series HARDWARE MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90570/A series HARDWARE MANUAL FUJITSU LIMITED PREFACE • Objectives and Intended Reader Thank you for your interest in Fujitsu semiconductor products.
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CM44-10102-5E
2MC-16LX
16-BIT
MB90570/A
-16LX
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DDA 003A
Abstract: CON12 M68HC11 MC68HC11C0 MC68HC11C0CFN2 MC68HC11C0CFU2 MC68HC11C0CFU3 MC68HC11C0FU3 MC68HC11C0MFU2 MC68HC11C0VFN2
Text: MOTOROLA Order this document by MC68HC11C0TS/D SEMICONDUCTOR TECHNICAL DATA MC68HC11C0 Technical Summary 8-Bit Microcontroller 1 Introduction The MC68HC11C0 high-performance microcontroller unit MCU is an enhanced member of the M68HC11 family of microcontrollers. Excluding its new features, the MC68HC11C0 is very similar to
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MC68HC11C0TS/D
MC68HC11C0
MC68HC11C0
M68HC11
MC68HC11E9
64Kbyte
MPC505TS/D
DDA 003A
CON12
MC68HC11C0CFN2
MC68HC11C0CFU2
MC68HC11C0CFU3
MC68HC11C0FU3
MC68HC11C0MFU2
MC68HC11C0VFN2
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1010001
Abstract: cordless phone design datasheet direct sequence spread spectrum P115 Z87000 Z87001 Z87010 Z87L01 cordless phone Transceiver IC TDD synchronizer
Text: PRELIMINARY PRODUCT SPECIFICATION 1 Z87001/Z87L01 1 ROMLESS SPREAD SPECTRUM CORDLESS PHONE CONTROLLER FEATURES Device ROM * kwords Z87001 Z87L01 64 64 RAM I/O (Words) Lines 512 512 32 32 Package Information • 144-Pin VQFP 144-Pin VQFP Note: *Maximum accessible external ROM
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Z87001/Z87L01
Z87001
Z87L01
144-Pin
DS96WRL0801
1010001
cordless phone design datasheet
direct sequence spread spectrum
P115
Z87000
Z87001
Z87010
Z87L01
cordless phone Transceiver IC
TDD synchronizer
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17CA
Abstract: M68HC16 MC16S2CPU20B1 MC16S2CPU25B1 MC68HC16S2 MC68HC16S2CPU20 MC68HC16S2CPU25 SPMC16S2CPU20 SPMC16S2CPU25 37A6
Text: Order this document by MC68HC16S2TS/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC68HC16S2 Technical Summary 16-Bit Modular Microcontroller 1 Introduction The MC68HC16S2 is a high-speed 16-bit microcontroller. It is a member of the MC68300/M68HC16 family. M68HC16 microcontrollers are built up from standard modules that interface through a common intermodule bus IMB . Standardization facilitates rapid development of devices tailored for specific applications.
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MC68HC16S2TS/D
MC68HC16S2
16-Bit
MC68HC16S2
MC68300/M68HC16
M68HC16
CPU16)
17CA
MC16S2CPU20B1
MC16S2CPU25B1
MC68HC16S2CPU20
MC68HC16S2CPU25
SPMC16S2CPU20
SPMC16S2CPU25
37A6
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MC2100 REV B
Abstract: MC2100 REV c 74109 MC2100 e rev b MC2100 Rev A MC212 MC2100 MC2300 MC2400 MC2500
Text: Navigator Motion Processor MC2100 Series Technical Specifications for Brushed Servo Motion Control Performance Motion Devices, Inc. 55 Old Bedford Road Lincoln, MA 01773 Revision 1.6, April 2002 NOTICE This document contains proprietary and confidential information of Performance Motion Devices,
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MC2100
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
CP2N40
UI0-10
UI0-11
MC2100 REV B
MC2100 REV c
74109
MC2100 e rev b
MC2100 Rev A
MC212
MC2300
MC2400
MC2500
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SPEAKERPHONE
Abstract: D6351A-11 D6305B D6351A KM29N040
Text: D6351A Flash TAD Chip for an all Digital Telephone Answering Device with True FULL Duplex SpeakerPhone General Description The D6351A chip is a digital speech/signal processing subsystem that implements all functions of TRUESPEECH speech compression and voice prompts, telephone line signal processing, flash memory management, and True FULL
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D6351A
D6351A
PO-12/96
SPEAKERPHONE
D6351A-11
D6305B
KM29N040
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STK 5333 s
Abstract: 1838 ir receiver b 010 22 05 feme MC68HC11KA4 STK 407 040 stk 4192 II 009C MC68HC711KA4
Text: MC68HC11KA4RG/AD MC68HC11KA4 MC68HC711KA4 PROGRAMMING REFERENCE GUIDE M m o t o r o l a Block Diagram PAI/0C1 PULSE ACCUMULATOR OC2/OC1 0C3/0C1 OC4/OC1 IC4/OC5/OC1 ICI IC2 IC3 P B 7 -< -> PB6 P B 5 < -> j m PB4 PB3 P B 2< -> 1 PB1 PBO ADDR15 ADDR14 ADDR13
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MC68HC11KA4RG/AD
MC68HC11KA4
MC68HC711KA4
MC68HC711KA4)
MC68HC11KA4RG/AD
STK 5333 s
1838 ir receiver
b 010 22 05 feme
STK 407 040
stk 4192 II
009C
MC68HC711KA4
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SuperSPARC
Abstract: Mbus master 250 slave circuit tmx390 STP1091-60
Text: S un M icroelectronics July 1997 Multi-Cache Controller DATA SHEET Integrated Cache Controller for SuperSPARC D e s c r ip t io n The STP1091 is a high-performance external cache controller for the STP1020 SuperSPARC and STP1021 (SuperSPARC-II) microprocessors. It is used when a large secondary cache or an interface to a non-MBus sys
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STP1091
STP1020
STP1021
33x8k
STP1091PGA-75
STP1091PGA-90
STP1020HS
STP1091
SuperSPARC
Mbus master 250 slave circuit
tmx390
STP1091-60
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3BL DBM
Abstract: 567 tone MODEL 2510 MICROPHONE CT8015 CT8015A11 DSP GROUP
Text: D S P G R O U P , TrueSpeech DSVD Co-Processor I NC . Introduction Features The CT8015 is a TrueSpeech co-processor capable of performing full duplex compression and de-compression functions for DSVD Digital Simultaneous Voice and Data Modems while maintaining M icrosoft Sound System 2.0 and
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CT8015
CT8015
concurrently11AQC
80-pin
3BL DBM
567 tone
MODEL 2510 MICROPHONE
CT8015A11
DSP GROUP
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WE32100
Abstract: ALI m7 101b WE32104
Text: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a mem ory-mapped peripheral device that performs memory-to-memory, memory fill, mem ory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that
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32-bit
133-pin
225pF)
WE32100
ALI m7 101b
WE32104
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