40B5
Abstract: 42B2 RT54SX-S TQ100
Text: v4.1 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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Silicon Sculptor II
Abstract: 40B5 42B2 RT54SX-S TQ100 180-pin
Text: v4.3 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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Untitled
Abstract: No abstract text available
Text: v4.2 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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LAYOUT FUSE
Abstract: actel ex128 f actel tq64
Text: A c t e l ’s e X F P G A s Enabling the “Wired” Lifestyle eX Family Selector Guide eX64 eX128 eX256 3,000 6,000 12,000 Dedicated Registers 64 128 256 • Standby/Static Current 2mA Combinatorial Cells 128 256 512 • Small footprint Maximum User I/Os
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TQ100,
CS128
eX128
eX256
CS128,
CS180
LAYOUT FUSE
actel ex128 f
actel tq64
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PMX32
Abstract: pqfp 3.2mm footprint a54sx72a
Text: Actel FPGA Selector Guide System Gates Typical Gates Logic Modules Dedicated FlipFlops Max FlipsFlops SRAM Bits Max I/O Available 2.5V CMOS Drive 3.3V CMOS Drive 5V CMOS Drive 5V Tolerant Inputs 3.3V PCI I/O 5V PCI I/O Slew Rate Control Routed Clocks HardWired
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FG1152
APA075
APA150
APA300
APA450
APA600
APA750
APA1000
AX125
AX250
PMX32
pqfp 3.2mm footprint
a54sx72a
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Silicon Sculptor II
Abstract: No abstract text available
Text: v4.0 eX Family FPGAs FuseLock Le a di n g E d ge P er f o r m a n ce • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad • No Power-Up/Down Sequence Required for Supply Voltages • Configurable Weak-Resistor Pull-Up or Pull-Down for
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antifuse programming technology
Abstract: EX256-TQ100
Text: Advanced v0.3 eX Family FPGAs Le a di n g E d ge P er f o r m a n ce • Configurable Weak-Resistor Pull-up or Pull-down for Tristated Outputs at Power Up • 240 MHz System Performance • 4.2 ns Clock-to-Out Pad-to-Pad • 3,000 to 12,000 Available System Gates
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EX256-TQ100
Abstract: No abstract text available
Text: v2.0.1 eX Family FPGAs Le a di n g E d ge P er f o r m a n ce • Configurable Weak-Resistor Pull-up or Pull-down for Tristated Outputs at Power Up • 240 MHz System Performance • 3.9 ns Clock-to-Out Pad-to-Pad • 3,000 to 12,000 Available System Gates
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Untitled
Abstract: No abstract text available
Text: v3.0 eX Family FPGAs Le a di n g E d ge P er f o r m a n ce • 240 MHz System Performance Sp e ci f i c a t i on s • Individual Output Slew Rate Control • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Software Design Support with Actel Designer Series and
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silicon sculptor
Abstract: 40B5 Silicon Sculptor II 42B2 RT54SX-S TQ100 180-pin actel EX128 TQ100 EX256-TQ100
Text: v4.2 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)
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EX256-TQ100
Abstract: No abstract text available
Text: Advanced v0.3 eX Family FPGAs Le a di n g E d ge P er f o r m a n ce • Configurable Weak-Resistor Pull-up or Pull-down for Tristated Outputs at Power Up • 240 MHz System Performance • 4.2 ns Clock-to-Out Pad-to-Pad • 3,000 to 12,000 Available System Gates
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CS180
Abstract: RT54SX-S TQ100 actel EX128 TQ100 actel package mechanical drawing EX256-TQ100
Text: v3.0 eX Family FPGAs Le a di n g E d ge P er f o r m a n ce • 240 MHz System Performance Sp e ci f i c a t i on s • Individual Output Slew Rate Control • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Software Design Support with Actel Designer Series and
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UA 796
Abstract: 40B5 42B2 RT54SX-S TQFP-64 PACKAGE thermal resistance bst web guiding uA796 UA 795
Text: Revision 9 eX Family FPGAs FuseLock Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)
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Untitled
Abstract: No abstract text available
Text: Revision 5 ex Automotive Family FPGAs Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops Using CC Macros • 0.22 m CMOS Process Technology • Up to 132 User-Programmable I/O Pins Features • Live on Power-Up • No Power-Up/Down Sequence Required for Supply
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Silicon Sculptor II
Abstract: No abstract text available
Text: A c t e l ’s e X F P G A s Enabling the “Wired” Lifestyle Have you had enough of the seemingly hopeless search for the ultimate low-cost solution for low-power, high-performance designs? The search is now over: Actel’s eX family of FPGAs has optimum circuit design capability
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TQ100,
CS128,
CS180
1-888-99-ACTEL
Silicon Sculptor II
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ACEQ100
Abstract: actel flashpro3 schematic actel a40mx02 actel EX128 TQ100 Actel A40MX04 FlashPro3 FG144 engine control module arm7 embedded c programming examples FG256
Text: Automotive Solutions FROM CONCEPT TO PRODUCTION Key Features Actel, the world’s leading supplier of high-reliability FPGAs, now offers the — Nonvolatile, High-Reliability industry’s broadest automotive product portfolio that addresses the unique needs of vehicle designers. FPGAs are being used today in under-the-hood
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reverse engineering
Abstract: cpld shelf life
Text: Application Examples Protect your Design: Secure your Set-top box Set-top box designers need to combine low manufacturing cost at very high volumes with reliability and security in order to create a successful product. With their leading high volume pricing and the protection
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IEEE1394.
32/64-bit
ADV7123
10-bit
25MHz
reverse engineering
cpld shelf life
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EX256-TQ100
Abstract: No abstract text available
Text: Revision 10 eX Family FPGAs Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)
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RT54SX72SCQ208
Abstract: A42MX16 RT54SX32S-CQ208 CQ208 CQ256
Text: v3.0 Component Selector Guide PCI 5.0 Volt Tolerant — 5 Volt I/O — Yes Yes Yes — — Yes 3.3 Volt I/O 3,000 2.5 Volt I/O Gates 36 JTAG I/O User I/O C, I SRAM Bits Screening –F, Std, –P Wide Decodes Speed Grade CS49 Flip-Flops/Dedicated Max Package
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CS128
TQ100
eX128
eX256
CS180
A54SX08A
RT54SX72SCQ208
A42MX16
RT54SX32S-CQ208
CQ208
CQ256
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