Untitled
Abstract: No abstract text available
Text: NXP level-shifting and hot-swappable I2C/SMBus buffers PCA9510A/11A/12B/13A/14A I2C/SMBus buffers for backplane multi-point and hot-swap applications These bus buffers isolate the backplane and card capacitance to permit the design of larger systems. They support live insertion with idle detect and precharge features, provide bidirectional
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PCA9510A/11A/12B/13A/14A
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AN10160
Abstract: dell MTBF "VME Backplane" MTBF vita38 intel motherboard wiring diagram A9512 IPMI "satellite management controller" PCA9510 PCA9511 PCA9512
Text: PCA9510/11/12/13/14 Level shifting and hot swappable I2C and SMBus bus buffers I2C master or slave devices Semiconductors PCA9510/11/12/13 or 14 Description Specifically designed for backplane multi-point and hot swap applications; the PCA9510/11/12/13/14/15 Hot Swappable Bus Buffers isolate the backplane
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PCA9510/11/12/13/14
PCA9510/11/12/13
PCA9510/11/12/13/14/15
AN10160
dell MTBF
"VME Backplane" MTBF
vita38
intel motherboard wiring diagram
A9512
IPMI "satellite management controller"
PCA9510
PCA9511
PCA9512
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vp44
Abstract: CY37064 CY37064V
Text: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -^ jjÉBT * ¿f5 ’00“’'* '^ 7“T{• < 1; .r - - •■■■■■■ c PRELIMINARY CY37064V 3, £ ,.* k v / k J UltraLogic 3.3V 64-Macrocell ISR™CLPD — tPD = 8.5ns Features — ts = 5.0 ns • 64 macrocells in four logic blocks
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CY37064V
64-Macrocell
vp44
CY37064
CY37064V
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L133A
Abstract: No abstract text available
Text: CY7C1346 64K X 36 Synchronous-Pipelined Cache RAM Features The C Y 7 C 1 346 I/O pins can op era te at eith er the 2.5V o r the 3.3V level; the I/O pins are 3.3 V to le ra n t w h en V DDQ=2.5V. • Supports 10O-MHz bus for Pentium and PowerPC operations with zero wait states
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CY7C1346
10O-MHz
166-MHz
133-MHz
100-MHz
L133A
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Untitled
Abstract: No abstract text available
Text: CY7C1327 256K X 18 Synchronous-Pipelined Cache RAM Features The CY7C1327 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V DDQ=2.5V. • Supports 1 0O-MHz bus for Pentium and PowerPC operations with zero wait states
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CY7C1327
166-MHz
133-MHz
100-MHz
CY7C1327
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Untitled
Abstract: No abstract text available
Text: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V DDQ=2.5V. • Supports 1 0O-MHz bus for Pentium and PowerPC operations with zero wait states
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CY7C1347
166-MHz
133-MHz
100-MHz
CY7C1347
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Untitled
Abstract: No abstract text available
Text: CY7C1346 PRELIMINARY 64K x 36 Synchronous-Pipelined Cache RAM Features T he C Y 7 C 1 346 I/O pins can o p era te at eith e r the 2.5 V o r the 3 .3 V level; the I/O pins are 3.3 V to le ra n t w h en V DDQ=2.5V. • S u p p o rts 1 0 0-M H z bus fo r P en tiu m and Pow erPC
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CY7C1346
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Untitled
Abstract: No abstract text available
Text: ww ww oooo oooo oooo oooo oooo oooo oooo oooooooooooc oooooooooooc oooooooooooc oooooooooooc oooo oooo oooo oooo oooo oooo oooo oooooooooooc oooooooooooc oooooooooooc oooooooooooc oooooooooooc 00000000000 o o o o o o o o o o o c i OOOOOOOOOOO oooooooooooc 500000000000
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PSC-4136
5M-1982
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ZERO VOLTAGE SWITCH
Abstract: No abstract text available
Text: July 1995 MÉLMicro Linear P R E L IM IN A R Y ML4822 ZVS Average Current PFC Controller GENERAL DESCRIPTION FEATURES The M L4822 is a PFC controller designed specifically for high power applications. The controller contains all of the functions necessary to implement an average current
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ML4822
L4822
A95131
ZERO VOLTAGE SWITCH
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FZH 261
Abstract: FZH 181 gal 16v8 programming algorithm FZH 201 VP16V8E-25 FZL 111 VP16V8 VP16V8EPC fzl 181
Text: I V L S I V P 1 6 V 8E TECHNOLOGY INC _72 D E =1300347 ODOD4QS b Ò T -4 lt'l3 47 PRELIMINARY GENERIC ARRAY LOGIC FEATURES • Replaces all series 20 bipolar PAL* devices — Output Drive 24 mA IOL • High performance CMOS technology Low Power: 90 mA Max Active
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Untitled
Abstract: No abstract text available
Text: SHHM & PRELIMINARY CY7C1335 32K X 32 Synchronous-Pipelined Cache RAM Features • S u p p o rts 1 0 0-M H z bus fo r P en tiu m and Pow erPC o p e ra tio n s w ith zero w a it states • F ully reg istered inp u ts and o u tp u ts fo r p ip elined o p e r
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CY7C1335
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TIC 2460
Abstract: i8088 ZZ13 14503B SMOS 1351F SED1351F0A
Text: SEDI 351 SED1351 GRAPHICS LCD CONTROLLER • DESCRIPTION The SED1351F is a graphics LCD controller capable of controlling medium to large resolution displays. It transfers data from MPU to external frame buffer RAM and converts this data to display signals for LCD
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SED1351
SED1351F
64K-bit
256K-bit
QFP15-100
TIC 2460
i8088
ZZ13
14503B
SMOS 1351F
SED1351F0A
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15FP
Abstract: DOR31
Text: CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features The CY7C1339 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 1 0O-MHz bus for Pentium and PowerPC operations with zero wait states
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CY7C1339
166-MHz
133-MHz
100-MHz
CY7C1339
15FP
DOR31
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Untitled
Abstract: No abstract text available
Text: CY7C1335 32K X 32 Synchronous-Pipelined Cache RAM Features • Supports 1 00-MHz bus for Pentium and PowerPC operations with zero wait states • Fully registered inputs and outputs for pipelined oper ation • 32K by 32 common I/O architecture • Single 3.3V power supply
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CY7C1335
00-MHz
133-MHz
100-MHz
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Untitled
Abstract: No abstract text available
Text: CY2308 CYPRESS 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by ca pacitive load on FBK input • Multiple configurations, see “Available CY2308 Config urations” table • Multiple low skew outputs — Output-output skew less than 250 ps
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CY2308
CY2308
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1XFH12n100
Abstract: transistor 13n80
Text: MbE D • 4bflb22b G O D D E S S 4 HIXY I X Y S CORP T - l V l S □IXYS Data Sheet No. 91532A October 1991 HiPerFET POWER MOSFETs N-Channel, High dv/dt, Low trr, HDMOS™ Fam ily C haracteristics Features * Low RDS{on HDMOS™ Process • Rugged Polysilicon Gate Ceil Structure
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4bflb22b
1532A
200ns)
IXFH12N100
IXFH10N100
IXFM12N100
IXFM10N100
1XFH12n100
transistor 13n80
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Untitled
Abstract: No abstract text available
Text: CY2308 3.3V Zero Delay Buffer Features • Zero input-output propagation delay, adjustable by ca pacitive load on FBK input • Multiple configurations, see “Available CY2308 Config urations” table • Multiple low skew outputs — Output-output skew less than 250 ps
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CY2308
16-pin
150-mil
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