Untitled
Abstract: No abstract text available
Text: Cascadable Amplifier 10 to 2000 MHz A35/ SMA35 V3 Features Product Image • MEDIUM OUTPUT LEVEL +9 dBm TYP. • WIDE POWER SUPPLY RANGE: +8 TO +20 VOLTS Description The A35 RF amplifier is a discrete thin film hybrid design, which incorporates the use of thin film manufacturing
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SMA35
MIL-STD-883
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CA35
Abstract: SMA35
Text: A35 / SMA35 Cascadable Amplifier 10 to 2000 MHz Rev. V3 Features Product Image • MEDIUM OUTPUT LEVEL +9 dBm TYP. • WIDE POWER SUPPLY RANGE: +8 TO +20 VOLTS Description The A35 RF amplifier is a discrete thin film hybrid design, which incorporates the use of thin film manufacturing
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SMA35
MIL-STD-883
CA35
SMA35
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A35-1
Abstract: CA35-1 SMA35-1
Text: Cascadable Amplifier 2 to 2400 MHz A35-1/ SMA35-1 V2 Features Product Image • AVAILABLE IN SURFACE MOUNT • ULTRA WIDE BANDWIDTH 1-2600 MHz TYP. • MEDIUM OUTPUT LEVEL +9.5 dBm (TYP.) Description The A35-1 RF amplifier is a discrete thin film hybrid design,
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A35-1/
SMA35-1
A35-1
MIL-STD-883
CA35-1
SMA35-1
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A35-1
Abstract: CA35-1 SMA35-1
Text: A35-1 / SMA35-1 Cascadable Amplifier 2 to 2400 MHz Rev. V2 Features Product Image • AVAILABLE IN SURFACE MOUNT • ULTRA WIDE BANDWIDTH 1-2600 MHz TYP. • MEDIUM OUTPUT LEVEL +9.5 dBm (TYP.) Description The A35-1 RF amplifier is a discrete thin film hybrid design,
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A35-1
SMA35-1
MIL-STD-883
CA35-1
SMA35-1
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SMA35
Abstract: CA35
Text: A35/SMA35 10 TO 2000 MHz CASCADABLE AMPLIFIER • MEDIUM OUTPUT LEVEL: +9 dBm TYP. · WIDE POWER SUPPLY RANGE: +8 TO +20 VOLTS Typical Performance @ 25°C Specifications (Rev. Date: 11/00)* Characteristics Typical Frequency Small Signal Gain (min.) Gain Flatness (max.)
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A35/SMA35
SMA35
SMA35
CA35
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CA35
Abstract: SMA35
Text: A35/SMA35 10 TO 2000 MHz CASCADABLE AMPLIFIER • MEDIUM OUTPUT LEVEL: +9 dBm TYP. · WIDE POWER SUPPLY RANGE: +8 TO +20 VOLTS Typical Performance @ 25°C Specifications (Rev. Date: 11/00)* Characteristics Typical Frequency Small Signal Gain (min.) Gain Flatness (max.)
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A35/SMA35
SMA35
CA35
SMA35
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A35-1
Abstract: CA35-1 SMA35-1 a35-1 TRANSISTOR
Text: A35-1/SMA35-1 2 TO 2400 MHz TO-8 CASCADABLE AMPLIFIER • AVAILABLE IN SURFACE MOUNT · ULTRA WIDE BANDWIDTH 1-2600 MHz TYP. · MEDIUM OUTPUT LEVEL +9.5 dBm (TYP.) Typical Performance @ 25°C Specifications (Rev. Date: 2/03)* Characteristics Typical Frequency
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A35-1/SMA35-1
A35-1
SMA35-1
CA35-1
A35-1
CA35-1
SMA35-1
a35-1 TRANSISTOR
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7805CT
Abstract: MOC5010 ip1717 UA741CN op amp TL081P LM3524N LM13080N 7824ct LM7915CK LM7905CK
Text: Master Designer Version 8.5 Component Library Reference Volume 2 October 1995 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means-electronic, mechanical, photocopying, recording, or otherwise-without the prior
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700-PK400A1
Abstract: 700-PK400-A1 199-FSMA11 NEMA P600 199-FSMA10 4 pole relay
Text: Bulletin 700 Control Relays Type P, PK, and PH Bulletin 700 S S S S Cat. No. 700-P400A1 Cat. No. 700DC-P200 S Cat. No. 700-PK400A1 Cat. No. 700-PH200 S Direct Drive Convertible Contact Cartridge Relays Type P, PK, and PH 600V Maximum AC/DC Overlapping Contact
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700-P400A1
700DC-P200
700-PK400A1
700-PH200
700-CP1
700-CPM
700-CPH
700-CPR
700-PS,
700-N31
700-PK400A1
700-PK400-A1
199-FSMA11
NEMA P600
199-FSMA10
4 pole relay
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A 68066
Abstract: 17141E 58614 relay LXML-PWC2 152935 LM80 LXW8-PW40 16256 1501-12 77261 led 3528 lumen
Text: LUXEON Rebel IES LM-80 Test Report Design Resource DR04 LUXEON Rebel IES LM-80 Test Report 1. Number of LED light sources tested Eighty or 160 units per test / 25 units reported. Units reported are selected as follows: a Units are assigned to nominal CCT bins of 2650K, 3000K, 3500K, 4000K, or 6000K.
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LM-80
2650K,
3000K,
3500K,
4000K,
6000K.
LXM8-PW27
2700K)
LXM8-PW30
A 68066
17141E
58614 relay
LXML-PWC2
152935
LM80 LXW8-PW40
16256
1501-12
77261
led 3528 lumen
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marking b28
Abstract: 72v3672l 72V3672
Text: 3.3 VOLT CMOS SyncBiFIFOTM 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 FEATURES • • • • • • • • • • • Memory storage capacity: IDT72V3652 – 2,048 x 36 x 2 IDT72V3662 – 4,096 x 36 x 2 IDT72V3672 – 8,192 x 36 x 2 Supports clock frequencies up to 100MHz
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IDT72V3652
IDT72V3662
IDT72V3672
IDT72V3652
IDT72V3662
100MHz
G9911-05,
G-0302-06,
G-0302-05,
marking b28
72v3672l
72V3672
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C65 004
Abstract: RBS 2111 A37 diode CA12 HI20201 HI2303 HI2303EVAL HI2303JCQ 5 pin reset ic ARB A36 1334
Text: HI2303 S E M I C O N D U C T O R Triple 8-Bit, 50 MSPS, Video A/D Converter With Clamp Function November 1997 Features Applications • Resolution 8-Bit ±1/2 LSB DL • Video Digitizing (Composite and Y-C) • Low Power Consumption (at 50 MSPS Typ) (Reference Current Excluded) . . . . . . . . . . . . . .500mW
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HI2303
500mW
HI2303
1-800-4-HARRIS
C65 004
RBS 2111
A37 diode
CA12
HI20201
HI2303EVAL
HI2303JCQ
5 pin reset ic ARB
A36 1334
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C65 004
Abstract: RBS 2111 b24 b03 b34 diode HI2303EVAL 5 pin reset ic ARB rev A00 diagram pinout A77 CL crt bw diagram diode sy 223
Text: HI2303 Data Sheet December 1998 File Number 4106.2 Triple 8-Bit, 50 MSPS, Video A/D Converter with Clamp Function Features The HI2303 is a highly integrated 8-bit, 3-channel analog-todigital converter that is designed for component like RGB digitizing applications. The internal DC Restore (video
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HI2303
HI2303
C65 004
RBS 2111
b24 b03
b34 diode
HI2303EVAL
5 pin reset ic ARB
rev A00 diagram pinout
A77 CL
crt bw diagram
diode sy 223
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HDR20x2
Abstract: bdm programmer semiconductor b46 conn 2x16 HDR connector TEXTOOL zif 40 pin socket HC08 HCS08 MON08 TSW-103-07-S-D
Text: PAS08P40B3256 User’s Manual HC S 08 Programming Adapter PAS08P40B3256UM Revision 0.1, June 2005 User’s Manual — PAS08P40B3256 HC(S)08 Programming Adapter PAS08P40B3256 Quick Start Guide The PAS08P40B3256 is a low-cost universal programming adapter for HC08
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PAS08P40B3256
PAS08P40B3256UM
HCS08
16-pin
MON08
HCS08
40-pin
HDR20x2
bdm programmer
semiconductor b46
conn 2x16
HDR connector
TEXTOOL zif 40 pin socket
HC08
TSW-103-07-S-D
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a21b6
Abstract: ISL37231
Text: 10.3125 Gb/s Retiming Dual-Channel Transceiver ISL37231 Features The ISL37231 is an advanced dual-channel, dual-simplex retimer for active copper cable applications. Endowed with sophisticated functions, such as media optimized PCB or Cable and adaptive equalization, de-emphasis, and signal
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ISL37231
ISL37231
FN8266
a21b6
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multiplier accumulator MAC code verilog
Abstract: multiplier accumulator MAC code VHDL algorithm MULT18X18 ispLEVER project Navigator b312 diode SUM30 SUM32 TN1057 vhdl code for floating point subtractor ieee floating point multiplier verilog
Text: LatticeECP-DSP sysDSP Usage Guide October 2005 Technical Note TN1057 Introduction This technical note discusses how to access the features of the LatticeECP -DSP sysDSP™ Digital Signal Processing Block described in the LatticeECP/EC Family data sheet. Designs targeting the sysDSP Block offer significant improvement over traditional LUT-based implementations. Table 14-1 provides an example of the
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TN1057
LFECP20E-5
LFEC20E-5
18x18
multiplier accumulator MAC code verilog
multiplier accumulator MAC code VHDL algorithm
MULT18X18
ispLEVER project Navigator
b312 diode
SUM30
SUM32
TN1057
vhdl code for floating point subtractor
ieee floating point multiplier verilog
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2N3904 A30
Abstract: 2N3904 A52 2N3904 a27 2N3904 B28 Mec R68 2N3904 A41 intel c206 MCH 2N3904 a26 intel c202 MCH 2N3904 B21
Text: R Intel 840 Chipset Platform Memory Expansion Card MEC Design Guide July 2000 Document Number: 298239-001 ® Intel 840 Chipset Platform MEC R Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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LD33
Abstract: multiplier accumulator MAC code verilog multiplier accumulator MAC code VHDL algorithm multiplier accumulator MAC code VHDL TN1140 b312 diode lattice xp2 LD33 F MULT18X18 b114 sum ld6
Text: LatticeXP2 sysDSP Usage Guide February 2007 Technical Note TN1140 Introduction This technical note discusses how to access the features of the LatticeXP2 sysDSP™ Digital Signal Processing Block described in the LatticeXP2 Family Data Sheet. Designs targeting the sysDSP Block can offer significant
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TN1140
XP2-17-7
18x18
LD33
multiplier accumulator MAC code verilog
multiplier accumulator MAC code VHDL algorithm
multiplier accumulator MAC code VHDL
TN1140
b312 diode
lattice xp2
LD33 F
MULT18X18
b114 sum ld6
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LD33
Abstract: multiplier accumulator MAC code VHDL algorithm multiplier accumulator MAC 16 BITS using code VHDL addition accumulator MAC code verilog MULT18X18ADDSUBSUMB multiplier accumulator MAC code VHDL b312 diode MULT18X18 LD48 ld45
Text: LatticeECP2/M sysDSP Usage Guide November 2008 Technical Note TN1107 Introduction This technical note discusses how to access the features of the LatticeECP2 and LatticeECP2M™ sysDSP™ Digital Signal Processing Block described in the LatticeECP2/M Family Data Sheet. Designs targeting the sysDSP Block can offer significant improvement over traditional LUT-based implementations. Table 14-1 provides an
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TN1107
ECP2-50-7
LD33
multiplier accumulator MAC code VHDL algorithm
multiplier accumulator MAC 16 BITS using code VHDL
addition accumulator MAC code verilog
MULT18X18ADDSUBSUMB
multiplier accumulator MAC code VHDL
b312 diode
MULT18X18
LD48
ld45
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sria0
Abstract: ACCUM48 b24 b03 MULT18X18 ACCUM18 LUT14-1 sroa10 ACCUM28 SUM26 b110-b111
Text: TN1057_01.2J Oct. 2005 LatticeECP/EC sysDSP 使用ガイド はじめに このテクニカルノートはLatticeECP/ECファミリ・データシートで説明されたLatticeECP-DSP sysDSP デ ジタル信号処理 ブロックの機能にアクセスする方法について議論します。sysDSPブロックを対象とする設
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TN1057
LUT14-1
LFECP20E-5
LFEC20E-5
18x18
36x36
sysDSPLatticeECP-DSPsysDSP14-1
sria0
ACCUM48
b24 b03
MULT18X18
ACCUM18
LUT14-1
sroa10
ACCUM28
SUM26
b110-b111
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PLM-96
Abstract: 80c196kb-compatible A45 interface
Text: Index INDEX # AD.COMMAND, 5-20, 9-1, 9-3, 9-5, C -l, C-2, C-4, C-8, C -ll, C-60 programming for A/D conversions, 9-5 AD.RESULT, 5-20, 5-21, 9-1, 9-3, 9-7, C-l, C-2, C-4, C-9, C-10, C-60, C-61 AD.TIME, 9-1, 9-3, 9-4, C -l, C-2, C-4, C -ll, C-12, C-37 ADO-15, B-2
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80C196KB-compatible
10-bit
number052-8119
PLM-96
A45 interface
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Untitled
Abstract: No abstract text available
Text: CMOS SyncBiFIFO 2 5 6 x 3 6 x 2, 5 1 2 x 3 6 x 2, 1,0 2 4 x 3 6 x 2 FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted • Two independent clocked FIFOs buffering data in oppo
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IDT723622
IDT723632
IDT723642
IDT723622-256
IDT723632-512
IDT723642-1
67MHz
PN120-1
PQ132-1
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Untitled
Abstract: No abstract text available
Text: HI2303 HARRIS S E M I C O N D U C T O R Triple 8-B it, 50 M SPS, Video A/D C onverter W ith C lam p Function November 1997 Features Applications • Resolution 8-Bit ±1/2 LSB DL • Video Digitizing (Composite and Y-C) • Low Power Consumption (at 50 MSPS Typ)
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HI2303
500mW
HI2303
1-800-4-HARRIS
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RDRAM SOP
Abstract: rdram clock generator concurrent RDRAM 72 RDRAM concurrent
Text: E2G1059-28-Y1 O K I Semiconductor M S M 5 7 1 8 C 5 / M P 5 7 Previous version: Jul. 1998 6 4 8 2 ~ 18Mb 2M x 9 & 64Mb (8M x 8) Concurrent RDRAM DESCRIPTION The 18/64-M egabit Concurrent Rambus DRAMs (RDRAM ) are extremely high-speed CMOS DRAMs organized as 2M or 8 M words by 8 or 9 bits. They are capable of bursting unlimited
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E2G1059-28-Y1
18/64-M
SHP32-P-1125-0
RDRAM SOP
rdram clock generator
concurrent RDRAM 72
RDRAM concurrent
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