ULTRA338012 Search Results

ULTRA338012 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
Ultra338012		Cypress Semiconductor	UltraLogic Very High Speed 12K (36K) Gate 3.3V CMOS FPGA		Scan	PDF

ULTRA338012 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
antifuse programmable cell Abstract: No abstract text available Text: 7c33812: October 9, 1995 Revision: October 25, 1995 ADVANCED INFORMATION Ultra338012 UltraLogict Very High Speed 12K 36K Gate 3.3V CMOS FPGA D Robust routing resources Features D Full 3.3V operation D Very high speed D D D D D D Ċ Loadable counter frequencies	Original	7c33812: Ultra338012 208pin 352pin Ultra38000t Ultra38000 7C3380121 Ultra3800, antifuse programmable cell	PDF
ALI chipset Ali 3516 Abstract: SEM 2006 6216 static ram sem 2005 ALI chipset Ali 3510 vl82c483 ali 3516 CMOS 5408 PAL Decoder 16L8 1K x 8 static ram Text: June 1996 Cypres Semiconductor Corporation NUMERIC DEVICE INDEX Document Number Device Number 5000 5000 3518 3518 3519 CY101E383 CY10E383 CY2071 CY2081 CY2250 3522 3509 CY2252 CY2254A 3510 CY2255 3517 CY2257 3520 CY2260 3511 3023 3024 3011 3013 3019 3006 3023	Original	CY101E383 CY10E383 CY2071 CY2081 CY2250 CY2252 CY2254A CY2255 CY2257 CY2260 ALI chipset Ali 3516 SEM 2006 6216 static ram sem 2005 ALI chipset Ali 3510 vl82c483 ali 3516 CMOS 5408 PAL Decoder 16L8 1K x 8 static ram	PDF
loadable counter Abstract: No abstract text available Text: CYPRESS Features • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays under 7 ns • Unparalleled FPGA performance for counters, data path, state machines,	OCR Scan	208-pin 352-pin 16-bit 7C338012-1 Ultra38000, loadable counter	PDF
Untitled Abstract: No abstract text available Text: T0 CYPRESS F eatures • Full 3.3V operation • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input -I- logic cell +• output delays under 7 ns • Unparalleled FPGA performance for	OCR Scan	208-pin 16-bit 00EBBB00BB0BBE00 00EEEB0E0E00EE00 000EE00E000BE000 00EE0EEBE000E000 EBEEHBEEE00EB0EE E0BBBBBBE00BBBBB EE0E0000E000EE0H 0EEEE0000000E000	PDF