MT4C1004
Abstract: No abstract text available
Text: M T4C1004J S 4 MEG X 1 DRAM (M IC R O N DRAM 4 MEG x 1 DRAM 5V, STANDARD OR SELF REFRESH • 1,024-cycle refresh distributed across 16ms (T4C1004J) or 128ms (M T4C1004J S only) • Industry-standard pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process
|
OCR Scan
|
PDF
|
T4C1004J
024-cycle
MT4C1004J)
128ms
MT4C1004J
20/26-Pin
MT4C1004
|
4c1004
Abstract: No abstract text available
Text: M IC R O N I T4C1004J S 4 MEG X 1 DRAM •ZMCONDUCTÜR IM C 4 MEG X 1 DRAM DRAM STANDARD OR SELF REFRESH FEATURES PIN ASSIGNMENT (Top View) • 1,024-cycle refresh distributed across 16ms (M T4C1004J) or 128ms (T4C1004J S only) • Industry-standard pinout, timing, functions and
|
OCR Scan
|
PDF
|
MT4C1004J
024-cycle
T4C1004J)
128ms
225mW
T4C1004J
20/26-Pin
4c1004
|
Untitled
Abstract: No abstract text available
Text: M ’ I C R O N 1 MEG X 1 FPM D R A M DRAM M T4C 1004J FEATURES • 1,024-cycle refresh distributed across 16ms M T4C1004J or 128ms (M T4C1004J L only) • Industry-standard pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process
|
OCR Scan
|
PDF
|
024-cycle
T4C1004J)
128ms
T4C1004J
1004J
20/26-Pin
A10CL
|
Untitled
Abstract: No abstract text available
Text: OBSOLETE 4 MEG x 1 FPM DRAM MICRON I TECHNOLOGY, INC. M T4C 1004J FEATURES • 1,024-cycle refresh distributed across 16ms T4C1004J or 128m s (M T4C1004J L only) • Industry-standard pinout, tim ing, functions and packages • H igh-perform ance CM OS silicon-gate process
|
OCR Scan
|
PDF
|
1004J
024-cycle
MT4C1004J)
T4C1004J
20/26-Pin
|
1004J
Abstract: No abstract text available
Text: M T4C1004J L 4 MEG X 1 DRAM DRAM 4 MEG X 1 DRAM LOW POWER, EXTENDED REFRESH FEATURES • Industry standard x l pinout, timing, functions and packages • High-performance, CM OS silicon-gate process • Single +5V ±10% power supply • All inputs, outputs and clocks are fully TTL
|
OCR Scan
|
PDF
|
T4C1004J
024-cycle
128ms
225mW
20-Pin
MT4C1004JL
1004J
|
MT4C1004
Abstract: No abstract text available
Text: T4C1004J S 4 MEG X 1 DRAM |U|K=RON DRAM 4 MEG X 1 DRAM FEATURES • 1,024-cycle refresh distributed across 16ms (M T4C1004J) or 128ms (T4C1004J S only) • Industry-standard pinout, tim ing, functions and packages • High-perform ance CM OS silicon-gate process
|
OCR Scan
|
PDF
|
MT4C1004J
024-cycle
T4C1004J)
128ms
T4C1004J
20/26-Pin
20-Pin
MT4C1004
|
l992
Abstract: S992 T4C1004JDJ-6
Text: l^ iiC R T4C1004J 4 MEG X 1 DRAM o r s j DRAM 4 MEG X 1 DRAM FAST PAGE MODE FEATURES • Industry standard x l pinout, timing, functions and packages • High-performance, CM OS silicon-gate process • Single +5V ±10% power supply • Low power, 3mW standby; 225m W active, typical
|
OCR Scan
|
PDF
|
MT4C1004J
024-cycle
20-Pin
60nsn
l992
S992
T4C1004JDJ-6
|
Untitled
Abstract: No abstract text available
Text: T4C1004J S 4 MEG X 1 DRAM MICRON • SEMCONOUCTOR. INC 4 MEG X 1 DRAM DRAM STANDARD OR SELF REFRESH Zl > FEATURES • 1,024-cycle refresh distributed across 16ms (T4C1004J) o r 128ms (T4C1004J S only) • Industry-standard pinout, timing, functions and
|
OCR Scan
|
PDF
|
MT4C1004J
024-cycle
MT4C1004J)
128ms
225mW
|
