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    SN54LV08 Search Results

    SN54LV08 Datasheets (13)

    Part ECAD Model Manufacturer Description Curated Type PDF
    SN54LV08 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN54LV08 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN54LV08 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN54LV08A Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN54LV08AFK Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN54LV08AFK Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATE Original PDF
    SN54LV08AJ Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN54LV08AJ Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATE Original PDF
    SN54LV08AW Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATES Original PDF
    SN54LV08AW Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATE Original PDF
    SN54LV08FK Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATE Original PDF
    SN54LV08J Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATE Original PDF
    SN54LV08W Texas Instruments QUADRUPLE 2-INPUT POSITIVE-AND GATE Original PDF

    SN54LV08 Datasheets Context Search

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    LV08A

    Abstract: A115-A C101 SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387I – SEPTEMBER 1997 – REVISED JULY 2003 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 13 4B 2 3 12 4A 4 11 4Y 10 3B 9 3A 5 6 7 8 SN54LV08A . . . FK PACKAGE


    Original     		PDF SN54LV08A, SN74LV08A SCLS387I SN54LV08A LV08A A115-A C101 SN54LV08A SN74LV08A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		PDF SN54LV08A, SN74LV08A SCLS387K 000-V A114-A) A115-A) SN54LV08A SN74LV08A

    A115-A

    Abstract: C101 LV08A SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		PDF SN54LV08A, SN74LV08A SCLS387K SN54LV08A SN74LAmplifiers A115-A C101 LV08A SN54LV08A SN74LV08A

    LV08A

    Abstract: 74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387F – SEPTEMBER 1997 – REVISED AUGUST 2002 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 2 13 4B 3 12 4A 4 11 4Y GND 10 3B 9 3A 5 6 7 8 SN54LV08A . . . FK PACKAGE


    Original     		PDF SN54LV08A, SN74LV08A SCLS387F 000-V A114-A) A115-A) SN54LV08A LV08A 74LV08A

    LV08A

    Abstract: 74LV08A A115-A C101 SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		PDF SN54LV08A, SN74LV08A SCLS387K SN54LV08A SN74L LV08A 74LV08A A115-A C101 SN54LV08A SN74LV08A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D Ioff Supports Partial-Power-Down Mode D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV08A, SN74LV08A SCLS387L

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV08A, SN74LV08A SCLS387L

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08, SN74LV08 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS186C − FEBRUARY 1993 − REVISED APRIL 1996 SN54LV08 . . . J OR W PACKAGE SN74LV08 . . . D, DB, OR PW PACKAGE TOP VIEW D EPIC  (Enhanced-Performance Implanted D D D D 1A 1B 1Y 2A 2B 2Y GND


    Original     		PDF SN54LV08, SN74LV08 SCLS186C SN54LV08 MIL-STD-883C,

    LV08A

    Abstract: A115-A C101 SN54LV08A SN74LV08A SN74LV08ARGYR 74LV08a
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D Ioff Supports Partial-Power-Down Mode D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV08A, SN74LV08A SCLS387L LV08A A115-A C101 SN54LV08A SN74LV08A SN74LV08ARGYR 74LV08a

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D Ioff Supports Partial-Power-Down Mode D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV08A, SN74LV08A SCLS387L 000-V A114-A) A115-A)

    A115-A

    Abstract: C101 LV08A SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		PDF SN54LV08A, SN74LV08A SCLS387K SN54LV08A SN74Ltrollers A115-A C101 LV08A SN54LV08A SN74LV08A

    LV08

    Abstract: SN74LV08 SN74LV08D SN74LV08DBLE SN74LV08DR SN74LV08PWLE SN54LV08
    Text: SN54LV08, SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS186C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV08, SN74LV08 SCLS186C MIL-STD-883C, JESD-17 300-mil SN54LV08 LV08 SN74LV08 SN74LV08D SN74LV08DBLE SN74LV08DR SN74LV08PWLE SN54LV08

    LV08A

    Abstract: A115-A C101 SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387E – SEPTEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV08A . . . J OR W PACKAGE SN74LV08A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		PDF SN54LV08A, SN74LV08A SCLS387E SN54LV08A 000-V A114-A) A115-A) LV08A A115-A C101 SN54LV08A SN74LV08A

    LV08A

    Abstract: SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387D – SEPTEMBER 1997 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV08A, SN74LV08A SCLS387D MIL-STD-883, LV08A SN54LV08A SN74LV08A

    A115-A

    Abstract: C101 LV08A SN54LV08A SN74LV08A
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387J − SEPTEMBER 1997 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A


    Original     		PDF SN54LV08A, SN74LV08A SCLS387J SN54LV08A A115-A C101 LV08A SN54LV08A SN74LV08A

    LV08

    Abstract: SN54LV08 SN74LV08 SN74LV08D SN74LV08DBLE SN74LV08DR SN74LV08PWLE
    Text: SN54LV08, SN74LV08 QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS186C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV08, SN74LV08 SCLS186C MIL-STD-883C, JESD-17 300-mil LV08 SN54LV08 SN74LV08 SN74LV08D SN74LV08DBLE SN74LV08DR SN74LV08PWLE

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387B – SEPTEMBER 1997 – REVISED MAY 1998 D EPIC Enhanced-Performance Implanted D D D D CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)


    Original     		PDF SN54LV08A, SN74LV08A SCLS387B MIL-STD-883, SN54LV08A SN74LV08A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		PDF SN54LV08A, SN74LV08A SCLS387K 000-V A114-A) A115-A) SN54LV08A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		PDF SN54LV08A, SN74LV08A SCLS387K 000-V A114-A) A115-A) SN54LV08A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D Ioff Supports Partial-Power-Down Mode D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV08A, SN74LV08A SCLS387L 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS387K − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y


    Original     		PDF SN54LV08A, SN74LV08A SCLS387K SN54LV08A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387L − SEPTEMBER 1997 − REVISED OCTOBER 2010 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D Ioff Supports Partial-Power-Down Mode D D <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV08A, SN74LV08A SCLS387L 000-V A114-A) A115-A)

    LS387

    Abstract: No abstract text available
    Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387B - SEPTEMBER 1997 - REVISED MAY 1998 EPICM Enhanced-Performance Implanted CMOS Process SN54LV08A . . . J OR W PACKAGE SN74LV08A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)


    OCR Scan     		PDF SN54LV08A, SN74LV08A SCLS387B JESD17 MIL-STD-883, 300-mil LS387

    LS186C

    Abstract: LS186
    Text: SN54LV08, SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATES S C LS 186C - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-ii Process SN54LV08 . . . J OR W PACKAGE SN74LV08 . . . D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)


    OCR Scan     		PDF SN54LV08, SN74LV08 MIL-STD-883C, JESD-17 300-mil SN54LV08 SN74LV08 LS186C LS186