SN54LV05A
Abstract: SN74LV05A
Text: SN54LV05A, SN74LV05A HEX INVERTERS WITH OPEN-DRAIN OUTPUTS SCLS391C – APRIL 1998 – REVISED OCTOBER 1998 D D D D D EPIC Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)
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SN54LV05A,
SN74LV05A
SCLS391C
MIL-STD-883,
SN54LV05A
SN54LV05A
SN74LV05A
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FT 4013 d dual flip flop
Abstract: FT 4013 D flip flop 74HC octal bidirectional latch 74HCT 4013 DATASHEET 4511 pin configuration SN7432 fairchild CMOS TTL Logic Family Specifications 7805 acv Datasheet of decade counter CD 4017 sn74154
Text: T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Logic Selection Guide February 2000 1999 EEProduct News PRODUCTS OF THE YEAR AWARD New products for prototype design AVC Advanced Very-Low-Voltage CMOS Logic See Section 4 LOGIC OVERVIEW 1 FUNCTIONAL INDEX
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T flip flop IC
Abstract: pin designation for CD40110B IC 74LS series logic gates 3 input or gate FT 4013 d dual flip flop ic cmos 4011 CD4001* using NAND gates IC CD 4033 pin configuration Quad 2 input nand gate cd 4093 FT 4013 D flip flop 74HCT 4013 DATASHEET
Text: T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Logic Selection Guide February 2000 1999 EEProduct News PRODUCTS OF THE YEAR AWARD New products for prototype design AVC Advanced Very-Low-Voltage CMOS Logic See Section 4 LOGIC OVERVIEW 1 FUNCTIONAL INDEX
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Untitled
Abstract: No abstract text available
Text: SN54LV05A, SN74LV05A HEX INVERTERS WITH OPEN-DRAIN OUTPUTS SCLS391C - APRIL 1998 - REVISED OCTOBER 1998 • EP/C Enhanced-Performance Implanted CMOS Process • Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C • • • •
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OCR Scan
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PDF
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SN54LV05A,
SN74LV05A
SCLS391C
MIL-STD-883,
SN54LV05A
SN74LV05A
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