Untitled
Abstract: No abstract text available
Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387B – SEPTEMBER 1997 – REVISED MAY 1998 D EPIC Enhanced-Performance Implanted D D D D CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)
|
Original
|
PDF
|
SN54LV08A,
SN74LV08A
SCLS387B
MIL-STD-883,
SN54LV08A
SN74LV08A
|
SN74 schmitt trigger
Abstract: SDYU001 SN54LV00A SN54LV02A SN54LV04A SN54LV05A SN54LV08A SN54LV14A SN54LV32A SN54LV74A
Text: LVC and LV LowĆVoltage CMOS Logic Data Book 1998 Logic Products General Information LVC Gates and MSI LVC Octals LVC Widebus LVC 3.3-V to 5-V Translators and Cable Drivers LV Gates and MSI LV Octals Application Reports Mechanical Data LVC and LV Low-Voltage CMOS Logic
|
Original
|
PDF
|
MIL-STD-1835
GDFP2-F20
SN74 schmitt trigger
SDYU001
SN54LV00A
SN54LV02A
SN54LV04A
SN54LV05A
SN54LV08A
SN54LV14A
SN54LV32A
SN54LV74A
|
transistor fn 1016
Abstract: SN74HC1G00 SCAD001D sn74154 SN74ALVC1G32 JK flip flop IC SDFD001B philips 18504 FB 3306 CMOS Data Book Texas Instruments Incorporated
Text: W O R L D L Logic Selection Guide August 1998 E A D E R I N L O G I C P R O D U C T S LOGIC OVERVIEW 1 FUNCTIONAL INDEX 2 FUNCTIONAL CROSSĆREFERENCE 3 DEVICE SELECTION GUIDE 4 3 LOGIC SELECTION GUIDE AUGUST 1998 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or
|
Original
|
PDF
|
|
LS387
Abstract: No abstract text available
Text: SN54LV08A, SN74LV08A QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS387B - SEPTEMBER 1997 - REVISED MAY 1998 EPICM Enhanced-Performance Implanted CMOS Process SN54LV08A . . . J OR W PACKAGE SN74LV08A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)
|
OCR Scan
|
PDF
|
SN54LV08A,
SN74LV08A
SCLS387B
JESD17
MIL-STD-883,
300-mil
LS387
|