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    D103D

    Abstract: x1sv 199S SN74LV02
    Text: SN74LV02 QUADRUPLE 2-INPUT POSITIVE-NOR GATE SCLS183A - FEBRUARY 1993 - REVISED JULY 1995 • EPIC Enhanced-Performance Implanted CMOS 2-n Process • Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C • Typical Vq hv (Output Vq h Undershoot)


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    SN74LV02 SCLS183A MIL-STD-883C, JESD-17 D103D31 D103D x1sv 199S SN74LV02 PDF