SN74AUC2G126DCTR
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
SN74AUC2G126DCTR
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A115-A
Abstract: C101 SN74AUC2G126 SN74AUC2G126YEPR SN74AUC2G126DCTR
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3ĆSTATE OUTPUTS SCES533A − DECEMBER 2003 − REVISED FEBRUARY 2004 D Available in the Texas Instruments D D D D D D D D DCT OR DCU PACKAGE TOP VIEW NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V
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SN74AUC2G126
SCES533A
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC2G126
SN74AUC2G126YEPR
SN74AUC2G126DCTR
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Untitled
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
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SN74AUC2G126DCTR
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533A – DECEMBER 2003 – REVISED MARCH 2005 FEATURES • • • • • • • • • DCT OR DCU PACKAGE TOP VIEW Available in the Texas Instruments NanoStar and NanoFree™ Packages
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Original
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PDF
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SN74AUC2G126
SCES533A
000-V
A114-A)
A115-A)
SN74AUC2G126DCTR
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A115-A
Abstract: C101 SN74AUC2G126 SN74AUC2G126DCTR
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC2G126
SN74AUC2G126DCTR
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Untitled
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
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SN74AUC2G126DCTR
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533A – DECEMBER 2003 – REVISED MARCH 2005 FEATURES • • • • • • • • • DCT OR DCU PACKAGE TOP VIEW Available in the Texas Instruments NanoStar and NanoFree™ Packages
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Original
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PDF
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SN74AUC2G126
SCES533A
000-V
A114-A)
A115-A)
SN74AUC2G126DCTR
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Untitled
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533A – DECEMBER 2003 – REVISED MARCH 2005 FEATURES • • • • • • • • • DCT OR DCU PACKAGE TOP VIEW Available in the Texas Instruments NanoStar and NanoFree™ Packages
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Original
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PDF
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SN74AUC2G126
SCES533A
000-V
A114-A)
A115-A)
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Untitled
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
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A115-A
Abstract: C101 SN74AUC2G126 SN74AUC2G126YEPR
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3ĆSTATE OUTPUTS SCES533A − DECEMBER 2003 − REVISED FEBRUARY 2004 D Available in the Texas Instruments D D D D D D D D DCT OR DCU PACKAGE TOP VIEW NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V
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Original
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PDF
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SN74AUC2G126
SCES533A
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC2G126
SN74AUC2G126YEPR
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Untitled
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
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SN74AUC2G126DCTR
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
SN74AUC2G126DCTR
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Untitled
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3ĆSTATE OUTPUTS SCES533 − DECEMBER 2003 D Available in the Texas Instruments D D D D D D D D DCT OR DCU PACKAGE TOP VIEW NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533
000-V
A114-A)
A115-A)
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SN74AUC2G126DCTR
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533B – DECEMBER 2003 – REVISED SEPTEMBER 2006 FEATURES • • • • • • Available in the Texas Instruments NanoStar and NanoFree™ Packages Optimized for 1.8-V Operation and Is 3.6-V I/O
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Original
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PDF
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SN74AUC2G126
SCES533B
000-V
A114-A)
A115-A)
SN74AUC2G126DCTR
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A115-A
Abstract: C101 SN74AUC2G126 74AUC SN74AUC2G126DCTR
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC2G126
74AUC
SN74AUC2G126DCTR
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A115-A
Abstract: C101 SN74AUC2G126 SN74AUC2G126DCTR
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533A – DECEMBER 2003 – REVISED MARCH 2005 FEATURES • • • • • • • • • DCT OR DCU PACKAGE TOP VIEW Available in the Texas Instruments NanoStar and NanoFree™ Packages
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Original
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PDF
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SN74AUC2G126
SCES533A
000-V
A114-A)
A115-A)
A115-A
C101
SN74AUC2G126
SN74AUC2G126DCTR
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SN74AUC2G126DCTR
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533B – DECEMBER 2003 – REVISED SEPTEMBER 2006 FEATURES • • • • • • Available in the Texas Instruments NanoStar and NanoFree™ Packages Optimized for 1.8-V Operation and Is 3.6-V I/O
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Original
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PDF
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SN74AUC2G126
SCES533B
000-V
A114-A)
A115-A)
SN74AUC2G126DCTR
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SN74AUC2G126DCTR
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
SN74AUC2G126DCTR
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SN74AUC2G126DCTR
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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Original
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PDF
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
SN74AUC2G126DCTR
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SN74AUC2G126DCTR
Abstract: No abstract text available
Text: SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS www.ti.com SCES533C – DECEMBER 2003 – REVISED JANUARY 2007 FEATURES • • • • • Available in the Texas Instruments NanoFree Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal
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SN74AUC2G126
SCES533C
000-V
A114-A)
A115-A)
SN74AUC2G126DCTR
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PLL WITH VCO 4046 appli note philips
Abstract: CD74HC4050 marking microstar ms 4011 CI 40106 8952 microcontroller ic 4017 decade counter datasheet ic HC 4066 AG GK 7002 7 SEGMENT DISPLAY LT 543 PIN CONFIGURATION LA 4508 as af power amplifier
Text: LOGIC OVERVIEW 1 PRODUCT INDEX 2 FUNCTIONAL CROSS−REFERENCE 3 DEVICE SELECTION GUIDE 4 PACKAGING AND MARKING INFORMATION A LOGIC PURCHASING TOOL/ALTERNATE SOURCES B LOGIC SELECTION GUIDE FIRST HALF 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,
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hp laptop MOTHERBOARD pcb CIRCUIT diagram
Abstract: hp laptop battery pack pinout SCBD002C hp laptop battery pinout sn74154 SN74LVC1G373 SDFD001B 4052 IC circuit diagram lg crt monitor circuit diagram PLL CD 4046
Text: LOGIC OVERVIEW 1 PRODUCT INDEX 2 FUNCTIONAL CROSS−REFERENCE 3 DEVICE SELECTION GUIDE 4 PACKAGING AND MARKING INFORMATION A LOGIC PURCHASING TOOL/ALTERNATE SOURCES B LOGIC SELECTION GUIDE SECOND HALF 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,
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