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    apr 8910

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108E – JULY 1997 – REVISED MARCH 2000 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		PDF SN74ALVC32 SCES108E MIL-STD-883, SN74ALVC32PWR SN74ALVC32 SCEM245, apr 8910

    MO-194

    Abstract: MPDS006C SN74ALVC32
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108E – JULY 1997 – REVISED MARCH 2000 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		PDF SN74ALVC32 SCES108E MIL-STD-883, MO-194 MPDS006C SN74ALVC32

    SN74ALVC32

    Abstract: No abstract text available
    Text: SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108E – JULY 1997 – REVISED MARCH 2000 D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)


    Original     		PDF SN74ALVC32 SCES108E MIL-STD-883, SN74ALVC32