SLLA067
Abstract: FB1650 FB2033A scea003a SN74FB2033K SN74FB2041A
Text: Application Report SCEA017 - April 2001 GTLP in BTL Applications Steve Blozis Standard Linear & Logic ABSTRACT This application report addresses the issues a designer might face when using a GTLP device in a BTL/FB+ application when a legacy BTL/FB+ bus implementation is still in use.
|
Original
|
PDF
|
SCEA017
20-slot
SLLA067
FB1650
FB2033A
scea003a
SN74FB2033K
SN74FB2041A
|
msi 7267 MOTHERBOARD SERVICE MANUAL
Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Text: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information
|
Original
|
PDF
|
GDFP1-F48
-146AA
GDFP1-F56
-146AB
msi 7267 MOTHERBOARD SERVICE MANUAL
ttl cookbook
msi ms 7267 MOTHERBOARD CIRCUIT diagram
"0.4mm" bga "ball collapse" height
PCF 799
crystal oscillator 8MHz 4 pins
smd diode MARKING F5 44C
smd TRANSISTOR code marking A7
terminals diagram of smd transistor bo2
cookbook for ic 555
|
A115-A
Abstract: C101 SN74GTLP1395 signal path designer
Text: www.ti.com SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY FEATURES • • • • • • • • • • • TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLP1395
A115-A
C101
SN74GTLP1395
signal path designer
|
Signal Path Designer
Abstract: No abstract text available
Text: SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLP2033
SCES352C
Signal Path Designer
|
A115-A
Abstract: C101 SN74GTLPH16927 SN74GTLPH16927GR
Text: SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS www.ti.com SCES413 – OCTOBER 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • • • • • • • DGG OR DGV PACKAGE TOP VIEW Member of the Texas Instruments Widebus
|
Original
|
PDF
|
SN74GTLPH16927
18-BIT
SCES413
A115-A
C101
SN74GTLPH16927
SN74GTLPH16927GR
|
A115-A
Abstract: C101 SN74GTLPH16927 SN74GTLPH16927GR
Text: SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS www.ti.com SCES413 – OCTOBER 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • • • • • • • DGG OR DGV PACKAGE TOP VIEW Member of the Texas Instruments Widebus
|
Original
|
PDF
|
SN74GTLPH16927
18-BIT
SCES413
A115-A
C101
SN74GTLPH16927
SN74GTLPH16927GR
|
A115-A
Abstract: C101 SN74GTLP2034 Signal path designer
Text: SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLP2034
SCES353C
A115-A
C101
SN74GTLP2034
Signal path designer
|
Untitled
Abstract: No abstract text available
Text: SN74GTLP2033 8ĆBIT LVTTLĆTOĆGTLP ADJUSTABLEĆEDGEĆRATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C − JUNE 2001 − REVISED SEPTEMBER 2001 DGG OR DGV PACKAGE TOP VIEW D Member of the Texas Instruments D D D D D D D D D D
|
Original
|
PDF
|
SN74GTLP2033
SCES352C
|
C101
Abstract: SN74GTLP2033 SN74GTLP2033DGGR Signal path designer
Text: SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLP2033
SCES352C
C101
SN74GTLP2033
SN74GTLP2033DGGR
Signal path designer
|
A115-A
Abstract: C101 SN74GTLP2034 Signal path designer
Text: SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLP2034
SCES353C
A115-A
C101
SN74GTLP2034
Signal path designer
|
Signal Path Designer
Abstract: No abstract text available
Text: SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLP2033
SCES352C
Signal Path Designer
|
MAX3234
Abstract: maxim dallas 2501 jtag gd75232 DALLAS 2501 jtag PL-2303 LGA 775 SOCKET PIN LAYOUT SN75176 PL-2303 SN75179 application MAX490 schematic
Text: R E A L W O R L D S I G N A L P TM R O C E S S I N G Interface Selection Guide 2Q 2004 Table of Contents Introduction .3 Data Line Circuits High-Speed Interconnect LVDS, xECL, CML .4
|
Original
|
PDF
|
RS-485/422.
RS-232.
MAX3234
maxim dallas 2501
jtag gd75232
DALLAS 2501
jtag PL-2303
LGA 775 SOCKET PIN LAYOUT
SN75176
PL-2303
SN75179 application
MAX490 schematic
|
Signal Path Designer
Abstract: No abstract text available
Text: SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLP2034
SCES353C
sdyu001x
scyb017a
scyt126
sceb005
Signal Path Designer
|
Signal Path Designer
Abstract: No abstract text available
Text: SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLP21395
SCES350C
Signal Path Designer
|
|
|
Signal path designer
Abstract: No abstract text available
Text: SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLP1395
SCES349C
SN74GTLP1395PW
SN74GTLP1395PWR
SN74GTLP1395
SCEM204,
Signal path designer
|
SIGNAL PATH designer
Abstract: No abstract text available
Text: SN74GTLP22034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES355B – JUNE 2001 – REVISED AUGUST 2001 D D D D D D D D D D D Member of Texas Instruments’ Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLP22034
SCES355B
SN74FB2033,
SIGNAL PATH designer
|
TTL 74 sl 90
Abstract: Signal Path Designer
Text: SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLP2033
SCES352C
TTL 74 sl 90
Signal Path Designer
|
signal path designer
Abstract: No abstract text available
Text: www.ti.com SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY FEATURES • • • • • • • • • • • TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLP1395
SCES349C
signal path designer
|
Untitled
Abstract: No abstract text available
Text: SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com FEATURES • • • • • • • • • • TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLP21395
SCES350C
|
Untitled
Abstract: No abstract text available
Text: www.ti.com SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY FEATURES • • • • • • • • • • • TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLP1395
SCES349C
|
SN74FB2033K
Abstract: No abstract text available
Text: SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion
|
Original
|
PDF
|
SN74FB2033K
SCBS472G
SN74FB2033KRC
SN74FB2033KRCR
|
SIGNAL PATH designer
Abstract: No abstract text available
Text: SN74GTLP22033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES354B – JUNE 2001 – REVISED AUGUST 2001 D D D D D D D D D D D Member of Texas Instruments’ Widebus Family TI-OPC Circuitry Limits Ringing on
|
Original
|
PDF
|
SN74GTLP22033
SCES354B
SN74FB2033.
SIGNAL PATH designer
|
signal path designer
Abstract: No abstract text available
Text: SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
|
Original
|
PDF
|
SN74GTLP1395
SCES349C
signal path designer
|
Untitled
Abstract: No abstract text available
Text: SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS www.ti.com SCES413 – OCTOBER 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • • • • • • • DGG OR DGV PACKAGE TOP VIEW Member of the Texas Instruments Widebus
|
Original
|
PDF
|
SN74GTLPH16927
18-BIT
SCES413
|