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    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER SCAS697 – JULY 2003 D Distributes One Differential Clock Input to VSS VDD0 Y0 Y0 VDD0 S1 24 23 22 21 20 19 15 Y1 VDDPECL 5 14 VDD1 VBB 6 13 VDD3 12 4 Y3 Y1 IN VDD2 IN 11


    Original     		PDF CDCM1804 SCAS697

    CDCM1804

    Abstract: G003
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E P0024-01 CDCM1804 G003

    CDCM1804

    Abstract: CDCM1804RTHR CDCM1804RTHT JESD51-7 SLUA271
    Text: CDCM1804 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER SCAS697C − JULY 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 VDDPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15


    Original     		PDF CDCM1804 SCAS697C CDCM1804 CDCM1804RTHR CDCM1804RTHT JESD51-7 SLUA271

    CDCM1804

    Abstract: G003
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E P0024-01 CDCM1804 G003

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER SCAS697B − JULY 2003 − REVISED DECEMBER 2003 D Distributes One Differential Clock Input to VSS Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4


    Original     		PDF CDCM1804 SCAS697B 800-MHz 200-MHz 24-Pin CDCM1804: scau009

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    CDCM1804

    Abstract: JESD51-7 SLUA271
    Text: CDCM1804 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER SCAS697C − JULY 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 VDDPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15


    Original     		PDF CDCM1804 SCAS697C CDCM1804 JESD51-7 SLUA271

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    CDCM1804

    Abstract: G003
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E P0024-01 CDCM1804 G003

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    QFN-24 reflow

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal QFN-24 reflow

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E 800-MHz 200-MHz 24-Terminal

    SLUA271

    Abstract: CDCM1804 G003 T006 T0069-01
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E P0024-01 CDCM1804 SLUA271 G003 T006 T0069-01

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER SCAS697C − JULY 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 VDDPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15


    Original     		PDF CDCM1804 SCAS697C 800-MHz 200-MHz 24-Pin

    Untitled

    Abstract: No abstract text available
    Text: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.


    Original     		PDF CDCM1804 SCAS697E P0024- CDCM1804