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    CDCF2510

    Abstract: CDCF2510PWR PC133 registered reference design CDC2509
    Text: CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz


    Original     		PDF CDCF2510 SCAS628B PC133 66MHz 24-Pin CDCF2510 CDCF2510PWR PC133 registered reference design CDC2509

    CDCF2510

    Abstract: CDCF2510PWR PC133 registered reference design
    Text: CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz


    Original     		PDF CDCF2510 SCAS628B PC133 66MHz 24-Pin CDCF2510 CDCF2510PWR PC133 registered reference design