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    A115-A

    Abstract: SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
    Text: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 D Designed to Ensure Defined Voltage Levels D D D D D D D D DW OR NS PACKAGE TOP VIEW on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation


    Original
    PDF SN74ACT1073 16-BIT SCAS193A 000-V A114-A) A115-A) A115-A SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR

    R-PDSO-G* Package

    Abstract: A115-A SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
    Text: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation


    Original
    PDF SN74ACT1073 16-BIT SCAS193A 000-V A114-A) A115-A) R-PDSO-G* Package A115-A SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR

    SN74ACT1071

    Abstract: SN74ACT1071D SN74ACT1071DE4 SN74ACT1071DG4 SN74ACT1071DR SN74ACT1071DRE4
    Text: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot


    Original
    PDF SN74ACT1071 10-BIT SCAS192 D3994, MIL-STD-883C, SN74ACT1071 SN74ACT1071D SN74ACT1071DE4 SN74ACT1071DG4 SN74ACT1071DR SN74ACT1071DRE4

    74ACT16475

    Abstract: 54ACT16475
    Text: 54ACT16475, 74ACT16475 18-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS198A – OCTOBER 1990 – REVISED APRIL 1996 D D D D D D D D Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Inverting Outputs Flow-Through Architecture Optimizes


    Original
    PDF 54ACT16475, 74ACT16475 18-BIT SCAS198A 500-mA 300-mil 25-mil 380-mil 25-mil ACT16475 74ACT16475 54ACT16475

    SN74ACT1071

    Abstract: d3994
    Text: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot


    Original
    PDF SN74ACT1071 10-BIT SCAS192 D3994, MIL-STD-883C, SN74ACT1071 d3994

    SN74ACT8994

    Abstract: PIN CONFIGURATION pci 32 bit 5 v
    Text: SN74ACT8994 DIGITAL BUS MONITOR IEEE STD 1149.1 JTAG SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER SCAS196E – JULY 1990 – REVISED DECEMBER 1996 D D D D D D D Member of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard


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    PDF SN74ACT8994 SCAS196E 1024-Word 16-Bit SN74ACT8994 PIN CONFIGURATION pci 32 bit 5 v

    SN74ACT1071

    Abstract: No abstract text available
    Text: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot


    Original
    PDF SN74ACT1071 10-BIT SCAS192 D3994, MIL-STD-883C, SN74ACT1071

    Untitled

    Abstract: No abstract text available
    Text: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 DW OR NS PACKAGE TOP VIEW D Designed to Ensure Defined Voltage Levels D D D D D D D D on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation


    Original
    PDF SN74ACT1073 16-BIT SCAS193A 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: 74AC11590 8ĆBIT BINARY COUNTER WITH REGISTERED 3ĆSTATE OUTPUTS ą SCAS194D3988, MARCH 1992 − REVISED APRIL 1993 • • • • • • • DW OR N PACKAGE TOP VIEW Parallel Registered Outputs Internal Counters Have Direct Clear Flow-Through Architecture Optimizes


    Original
    PDF 74AC11590 SCAS194 D3988, 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot


    Original
    PDF SN74ACT1071 10-BIT SCAS192 D3994, MIL-STD-883C,

    74ACT16475

    Abstract: No abstract text available
    Text: 54ACT16475, 74ACT16475 18-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS198A – OCTOBER 1990 – REVISED APRIL 1996 D D D D D D D D Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Inverting Outputs Flow-Through Architecture Optimizes


    Original
    PDF 54ACT16475, 74ACT16475 18-BIT SCAS198A 500-mA 300-mil 25-mil 380-mil 54ACT16475

    Untitled

    Abstract: No abstract text available
    Text: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199B – JANUARY 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized


    Original
    PDF SN74ACT7813 SCAS199B 50-pF SN74ACT78

    74AC11590

    Abstract: No abstract text available
    Text: 74AC11590 8-BIT BINARY COUNTER WITH REGISTERED 3-STATE OUTPUTS SCAS194D3988, MARCH 1992 – REVISED APRIL 1993 • • • • • • • DW OR N PACKAGE TOP VIEW Parallel Registered Outputs Internal Counters Have Direct Clear Flow-Through Architecture Optimizes


    Original
    PDF 74AC11590 SCAS194 D3988, 500-mA 300-mil 74AC11590

    Untitled

    Abstract: No abstract text available
    Text: 74ACT11590 8ĆBIT BINARY COUNTER WITH REGISTERED 3ĆSTATE OUTPUTS ą SCAS195D3989, MARCH 1992 − REVISED APRIL 1993 • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Parallel Registered Outputs Internal Counters Have Direct Clear


    Original
    PDF 74ACT11590 SCAS195 D3989, 500-mA 300-mil

    act7813

    Abstract: No abstract text available
    Text: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199B – JANUARY 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized


    Original
    PDF SN74ACT7813 SCAS199B 50-pF SN74ACT78struments act7813

    Untitled

    Abstract: No abstract text available
    Text: SN74ACT7803 512 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS191C – MARCH 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized


    Original
    PDF SN74ACT7803 SCAS191C 50-pF SN74ACT78struments

    Untitled

    Abstract: No abstract text available
    Text: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot


    Original
    PDF SN74ACT1071 10-BIT SCAS192 D3994, MIL-STD-883C,

    w65 transistor

    Abstract: SN74ACT7803 SN74ACT7805 SN74ACT7813
    Text: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199 – JANUARY 1991 – REVISED APRIL 1992 • • • • • • • • • • • • • Member of the Texas Instruments Widebus  Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident


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    PDF SN74ACT7813 SCAS199 50-pF w65 transistor SN74ACT7803 SN74ACT7805 SN74ACT7813

    A115-A

    Abstract: SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR
    Text: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation


    Original
    PDF SN74ACT1073 16-BIT SCAS193A 000-V A114-A) A115-A) A115-A SN74ACT1073 SN74ACT1073DW SN74ACT1073DWR SN74ACT1073NSR

    Untitled

    Abstract: No abstract text available
    Text: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199B – JANUARY 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized


    Original
    PDF SN74ACT7813 SCAS199B 50-pF

    Untitled

    Abstract: No abstract text available
    Text: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation


    Original
    PDF SN74ACT1073 16-BIT SCAS193A 000-V A114-A) A115-A)

    SN74ACT7803

    Abstract: SN74ACT7805 SN74ACT7813
    Text: SN74ACT7803 512 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS191 - MARCH 1991 - REVISED MARCH 1992 DL PACKAGE TOP VIEW • Member of the Texas Instruments W id e b u s F a m ily • Free-Running Read and Write Clocks Can Be Asynchronous or Coincident U 56


    OCR Scan
    PDF SN74ACT7803 SCAS191 50-pF Tbl723 6S8303 SN74ACT7803 SN74ACT7805 SN74ACT7813

    JW333

    Abstract: lm 7803
    Text: SN74ACT7803 512 x 1 8 C L O C K E D FIRST-IN, FI RS T - OU T M E M O R Y SCAS191A - MARCH 1991 - REVISED JULY 1995 DL PACKAGE I TOP VIEW I 1 1 • M e m b e r o f the Texas I n s t r u m e n t s W i d e b u s F ami ly I I • F re e - R un n i n g Read and Wr i te C l o c k s Can


    OCR Scan
    PDF SN74ACT7803 SCAS191A JW333 lm 7803

    Untitled

    Abstract: No abstract text available
    Text: 512 x SN74ACT7803 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS191C - MARCH 1991 - REVISED APRIL 1998 • • • • • Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized


    OCR Scan
    PDF SN74ACT7803 SCAS191C