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    SCAS144

    Abstract: No abstract text available
    Text: 74ACT11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER SCAS144 – OCTOBER 1990 – REVISED APRIL 1993 • • • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs


    Original     		PDF 74ACT11898 10-BIT SCAS144 500-mA 300-mil SCAS144

    Untitled

    Abstract: No abstract text available
    Text: 74ACT11898 10ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTER ą ą SCAS144 − OCTOBER 1990 − REVISED APRIL 1993 • • • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs


    Original     		PDF 74ACT11898 SCAS144 500-mA 300-mil

    SCAS144

    Abstract: 74ACT11898 74ACT11898DW
    Text: 74ACT11898 10ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTER ą ą SCAS144 − OCTOBER 1990 − REVISED APRIL 1993 • • • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs


    Original     		PDF 74ACT11898 10BIT SCAS144 500-mA 300-mil 74ACT11898 74ACT11898DW

    74ACT11898

    Abstract: SCAS144
    Text: 74ACT11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER SCAS144 – OCTOBER 1990 – REVISED APRIL 1993 • • • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs


    Original     		PDF 74ACT11898 10-BIT SCAS144 500-mA 300-mil 74ACT11898 SCAS144

    Untitled

    Abstract: No abstract text available
    Text: 74ACT11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER SCAS144 – OCTOBER 1990 – REVISED APRIL 1993 • • • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs


    Original     		PDF 74ACT11898 10-BIT SCAS144 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: 74ACT11898 10ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTER ą ą SCAS144 − OCTOBER 1990 − REVISED APRIL 1993 • • • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs


    Original     		PDF 74ACT11898 10BIT SCAS144 500-mA 300-mil