m6m72561
Abstract: 68-PIN M6M72561J-1
Text: I taM^AES 0015321 1 | MITSUBISHI LSIs MITSUBISHI -CMEMORV/ A S I O ObE D M6M72561J V E R S A T ILE ROM ~ 7Z DESCRIPTION Th e M 6M 72561J is a versatile RO M fabricated using the - / 3 - 3 S PIN CO N FIGU RATIO N TOP VIEW silicon gate C M O S process. It is housed in a 68-pin P L C C .
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M6M72561J
72561J
68-pin
16K-bit
m6m72561
M6M72561J-1
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs M6M72561J,-! VER SA TILE ROM DESCRIPTION The M 6 M 7 2 5 6 1 J is a versatile R O M fa b ric a te d using the PIN CONFIGURATION TOP VIEW s ilic o n gate C M OS process. I t is housed in a 6 8 -p in PLCC. •t ■ a. a. i : t i i : i : : The M 6 M 7 2 5 6 1 J has a 2 5 6 K -b it O T P R O M (One T im e
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OCR Scan
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PDF
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M6M72561J
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs M6M72561J,-! V E R S A T IL E ROM DESCRIPTION The M 6 M 7 2 5 6 1 J is a versatile R O M fa b ric a te d using the s ilic o n gate C M OS process. I t is housed in a 6 8 -pin PLCC. T he M 6 M 7 2 5 6 1 J has a 2 5 6 K -b it O T P R O M One T im e
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OCR Scan
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PDF
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M6M72561J
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