L64706
Abstract: receiver qpsk schematic diagram BPSK demodulator A/M29F010B(45/70/90/MT352/CG/NEC LSI QPSK
Text: L64706 Variable Rate QPSK/BPSK Demodulator Preliminary Specification L64706.TAR.3 Draft 5/19/95 Draft 5/19/95 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the
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L64706
DB14-000001-00
D-102
receiver qpsk schematic diagram
BPSK demodulator
A/M29F010B(45/70/90/MT352/CG/NEC LSI QPSK
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32QAM BLOCK DIAGRAM
Abstract: L64767 L64768
Text: L64768 QAM Demodulator and FEC Decoder Specification Rev-1.0 L64768.TAR.3 8/13/98 Preliminary This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the functional descriptions, or the electrical and mechanical specifications using
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L64768
DB14-000024-00,
July1997)
32QAM BLOCK DIAGRAM
L64767
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L64005
Abstract: l64002 L64007 L64108 LSI L64002 L64008 raytheon 2916 l64108 54 LSI L64108 L64005F
Text: L64005 Enhanced MPEG-2 Audio/Video Decoder Technical Manual Final Edition May 1998 This document contains proprietary information of LSI Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Corporation.
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L64005
DB14-000045-00,
L64005.
l64002
L64007
L64108
LSI L64002
L64008
raytheon 2916
l64108 54
LSI L64108
L64005F
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MR4010
Abstract: mr4010 equivalent MR4010 circuit MUX31H LSI coreware library B010 R3000 R4000 LCB500K CW4010
Text: MiniRISC MR4010 Superscalar Microprocessor Reference Device Contents 1 2 3 4 5 6 7 8 9 MR4010 Features MR4010 Functional Blocks 2.1 CW4010 Shell 2.2 Synchronous DRAM Controller DRAMC 2.3 SCbus to Local I/O Bus (Lbus) Controller (SCLC) 2.4 PLL Clock Circuit
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MR4010
MR4010
CW4010
mr4010 equivalent
MR4010 circuit
MUX31H
LSI coreware library
B010
R3000
R4000
LCB500K
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L64005
Abstract: L64002 Reed Solomon decoders with erasures msc 5530 schematic diagram CONVERTOR SATELLITE L64007 schematic diagram MODEM CONVERTOR SATELLITE L64704 l6470 sulzer pump
Text: L64704 Satellite Decoder Technical Manual May 1997 Order Number I14010.A May 1997 Document DB14-000026-01, Second Edition May 1997 This document describes Revision A of LSI Logic Corporation’s L64704 Satellite Decoder and will remain the official reference source for all revisions of this product until rescinded by an update.
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L64704
I14010
DB14-000026-01,
L64005
L64002
Reed Solomon decoders with erasures
msc 5530
schematic diagram CONVERTOR SATELLITE
L64007
schematic diagram MODEM CONVERTOR SATELLITE
l6470
sulzer pump
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TACHYON
Abstract: HPFC-5000
Text: TACHYON Fibre Channel Interface Controller Technical Data HPFC-5000 Features • Supports 1063, 531, and 266 Mbaud Link Speeds • Supports Fibre Channel Class 1, 2, and 3 Services • Supports Fibre Channel Arbitrated Loop FC-AL , Point-to-Point, and Fabric
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HPFC-5000
5965-6495E
TACHYON
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scsi-3
Abstract: No abstract text available
Text: Draft 12/9/96 LSI LOGIC Bidirectional 3.3 V I/O Buffer for SCSI-2, SCSI-3, and SCSI-3 Fast-20 Buses LCB500K Prelim inary Datasheet Description LSI Logic’s bidirectional buffer for SCSI is used to transmit and receive data on a SCSI-2 or SCSI-3 bus. The bus operates at rates up to 20 MHz. It can have 36 signals switching simul
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Fast-20
LCB500K)
Fast-20re
scsi-3
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jk 13001 TRANSISTOR
Abstract: jk 13001 13001 S 6D TRANSISTOR jk 13001 h signo 723 operation manual jk 13001 E bd4 lsi logic 0 281 020 099 SIS transistors 13001 s bd 13001 S 6D TRANSISTOR circuit
Text: LSI LOGIC LCA500K Prelim inary D esig n M anual June 1995 S304 A0 4 O O n s t M h3? This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.
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LCA500K
043/G
LCA500K
jk 13001 TRANSISTOR
jk 13001
13001 S 6D TRANSISTOR
jk 13001 h
signo 723 operation manual
jk 13001 E
bd4 lsi logic
0 281 020 099 SIS
transistors 13001 s bd
13001 S 6D TRANSISTOR circuit
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HPFC-5000
Abstract: TACHYON
Text: W h a l HEW LETT WULM P A C K A R D TACHYON Fibre Channel Interface C ontroller Technical Data HPFC-5000 Features • Supports 1063, 531, and 266 Mbaud Link Speeds • Supports Fibre Channel Class 1, 2, and 3 Services • Supports Fibre Channel Arbitrated Loop FC-AL ,
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HPFC-5000
5965-6495E
4447SAM
HPFC-5000
TACHYON
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Untitled
Abstract: No abstract text available
Text: LSI LOGIC CW900006 Triple 10-bit Video Cell LCB/LEA500K Advance Datasheet Introduction The CW900006 is a complete triple 10-bit video digital-to-analog converter VDAC that is implemented as a standard cell in LSI Logic’s 0.5 jam 500K process technology. It is designed
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CW900006
10-bit
LCB/LEA500K
LCB500K
LEA500K
75-ohm
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