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    Integrated Device Technology Inc IDTCSPUA877ABVG

    CSPUA877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components IDTCSPUA877ABVG 100
    • 1 $4.95
    • 10 $2.475
    • 100 $2.145
    • 1000 $2.145
    • 10000 $2.145
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    IDTCSPUA877A Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    IDTCSPUA877A Integrated Device Technology 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER Original PDF
    IDTCSPUA877ABVG Integrated Device Technology 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER Original PDF
    IDTCSPUA877ABVG8 Integrated Device Technology Clock/Timing - Application Specific, Integrated Circuits (ICs), IC PLL CLK DVR SDRAM 52-CABGA Original PDF
    IDTCSPUA877ANLG Integrated Device Technology 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER Original PDF
    IDTCSPUA877ANLG8 Integrated Device Technology Clock/Timing - Application Specific, Integrated Circuits (ICs), IC PLL CLK DVR SDRAM 40-VFQFPN Original PDF

    IDTCSPUA877A Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    ICS97ULP877

    Abstract: ICS98ULPA877A ICSSSTUB32872A IDTCSPUA877A MO-205 SSTU32864
    Text: ICSSSTUB32872A Integrated Circuit Systems, Inc. Advance Information 28-Bit Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A • Optimized for DDR2 400/533/667 JEDEC 4 Rank


    Original     		ICSSSTUB32872A 28-Bit ICS98ULPA877A, ICS97ULP877, IDTCSPUA877A SSTU32864 IDTCSPUA877A" ICS97ULP877 ICS98ULPA877A ICSSSTUB32872A IDTCSPUA877A MO-205 SSTU32864 PDF

    Untitled

    Abstract: No abstract text available
    Text: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A FEATURES: DESCRIPTION: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 Double Data Rate


    Original     		IDTCSPUA877A 125MHz 410MHz 52-Ball 40-pin IDTCSPUA877A CSPUA877A PDF

    Untitled

    Abstract: No abstract text available
    Text: IDTCSPUA877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPUA877A FEATURES: DESCRIPTION: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 Double Data Rate


    Original     		IDTCSPUA877A 125MHz 410MHz 52-Ball 40-pin CSPUA877A PDF

    Untitled

    Abstract: No abstract text available
    Text: ICSSSTUB32871A Integrated Circuit Systems, Inc. 27-Bit Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A • Optimized for DDR2 400/533/667 JEDEC 4 Rank


    Original     		ICSSSTUB32871A 27-Bit ICS98ULPA877A, ICS97ULP877, IDTCSPUA877A SSTU32864 ULP877 ULPA877A, PDF

    IDTCSPUA877A

    Abstract: ICS98ULPA877A IDT74SSTUBF32868A
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description occurred on the open-drain QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity,


    Original     		28-BIT cyc284 199707558G IDTCSPUA877A ICS98ULPA877A IDT74SSTUBF32868A PDF

    ICS98ULPA877A

    Abstract: ICSSSTUAF32868A IDTCSPUA877A
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description ICSSSTUAF32868A QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity


    Original     		28-BIT ICSSSTUAF32868A before284 199707558G ICS98ULPA877A ICSSSTUAF32868A IDTCSPUA877A PDF

    J2 Q24A B

    Abstract: Q24A ICS98ULPA877A ICSSSTUAF32868B IDTCSPUA877A q9bq12b
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs


    Original     		28-BIT enters284 199707558G J2 Q24A B Q24A ICS98ULPA877A ICSSSTUAF32868B IDTCSPUA877A q9bq12b PDF

    ICS98ULPA877A

    Abstract: IDT74SSTUBF32866B IDTCSPUA877A Q11A
    Text: DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description CONFIDENTIAL IDT74SSTUBF32866B design of the IDT74SSTUBF32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is


    Original     		25-BIT IDT74SSTUBF32866B IDT74SSTUBF32866B 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A Q11A PDF

    ICS98ULPA877A

    Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
    Text: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and


    Original     		IDT74SSTUBF32865A 28-BIT IDT74SSTUBF32865A 199707558G ICS98ULPA877A IDTCSPUA877A Q19A PDF

    ICS98ULPA877A

    Abstract: ICSSSTUAF32865A IDTCSPUA877A Q19A
    Text: DATASHEET ICSSSTUAF32865A 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description The ICSSSTUAF32865A includes a parity checking function. The ICSSSTUAF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates


    Original     		ICSSSTUAF32865A 28-BIT ICSSSTUAF32865A CL284 199707558G ICS98ULPA877A IDTCSPUA877A Q19A PDF

    ICS98ULPA877A

    Abstract: IDT74SSTUBF32865A IDTCSPUA877A Q19A
    Text: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and


    Original     		IDT74SSTUBF32865A 28-BIT IDT74SSTUBF32865A 199707558G ICS98ULPA877A IDTCSPUA877A Q19A PDF

    ICS98ULPA877A

    Abstract: ICSSSTUAF32869A IDTCSPUA877A Q11A SSTU32864
    Text: DATASHEET ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with


    Original     		ICSSSTUAF32869A 14-BIT ICSSSTUAF32869A 199707558G ICS98ULPA877A IDTCSPUA877A Q11A SSTU32864 PDF

    220v AC voltage stabilizer schematic diagram

    Abstract: LG color tv Circuit Diagram tda 9370 1000w inverter PURE SINE WAVE schematic diagram schematic diagram atx Power supply 500w TV SHARP IC TDA 9381 PS circuit diagram wireless spy camera 9744 mini mainboard v1.2 sony 279-87 transistor E 13005-2 superpro lx
    Text: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 AD9272 Analog Front End, iMEMS Accelerometers & Gyroscopes . . . . . . 782, 2583 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-528 Acceleration and Pressure Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2585


    Original     		AD9272 P462-ND LNG295LFCP2U P463-ND LNG395MFTP5U 220v AC voltage stabilizer schematic diagram LG color tv Circuit Diagram tda 9370 1000w inverter PURE SINE WAVE schematic diagram schematic diagram atx Power supply 500w TV SHARP IC TDA 9381 PS circuit diagram wireless spy camera 9744 mini mainboard v1.2 sony 279-87 transistor E 13005-2 superpro lx PDF

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs


    Original     		28-BIT enters284 199707558G PDF

    7105 CK DATASHEET

    Abstract: ICS98ULPA877A IDT74SSTUBH32868A IDTCSPUA877A Q24A Q16A J2 Q24A B
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description occurred on the open-drain QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity,


    Original     		28-BIT cyc284 199707558G 7105 CK DATASHEET ICS98ULPA877A IDT74SSTUBH32868A IDTCSPUA877A Q24A Q16A J2 Q24A B PDF

    ICS98ULPA877A

    Abstract: ICSSSTUAF32866C IDTCSPUA877A
    Text: DATASHEET ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is


    Original     		ICSSSTUAF32866C 25-BIT ICSSSTUAF32866C 14-bit 199707558G ICS98ULPA877A IDTCSPUA877A PDF

    160-ball

    Abstract: No abstract text available
    Text: DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and


    Original     		28-BIT IDT74SSTUBF32865A IDT74SSTUBF32865A 74SSTUBF32865ABK BK160) 74SSTUBF32865ABK8 160-ball PDF

    THL W8

    Abstract: No abstract text available
    Text: DATASHEET ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with


    Original     		14-BIT ICSSSTUAF32869A ICSSSTUAF32869A 199707558G THL W8 PDF

    IDT82V1671AJ

    Abstract: idt7164l85l32b IDT71256SA15YGI IDT7164L70L32B IDT7130SA55JG IDTQS3VH257S1 IDT71256L85L32B IDT74FCT163245CPA IDT71256L35YGI IDT71V3578S133PFGI
    Text: Integrated Device Technology, Inc. 6024 Silver Creek Valley Road, San Jose, CA 95138 PRODUCT/PROCESS CHANGE NOTICE PCN PCN #: TB-0512-01 DATE: 16-Dec-2005 MEANS OF DISTINGUISHING CHANGED DEVICES: Product Affected: All IDT Products Shipped in Product Mark


    Original     		TB-0512-01 16-Dec-2005 16-Dec-2005 sh5LV919-160J IDTQS3384PA IDTQS3VH16212PA IDTQS3VH257Q IDTQS5LV919-160JG IDTQS3384PAG IDTQS3VH16212PAG IDT82V1671AJ idt7164l85l32b IDT71256SA15YGI IDT7164L70L32B IDT7130SA55JG IDTQS3VH257S1 IDT71256L85L32B IDT74FCT163245CPA IDT71256L35YGI IDT71V3578S133PFGI PDF

    sumitomo g760

    Abstract: sumitomo EME G760 SUMITOMO EME G770 IDT75N43102S50BCG KMC-3580 EME-G770 IDT75N414S125BC IDT70T653MS12BCG JESD22-B116 IDT75N43102S62BCG
    Text: Integrated Device Technology, Inc. 6024 Silver Creek Valley Road, Dan Jose, CA 95138 PRODUCT/PROCESS CHANGE NOTICE PCN PCN #: A-0607-05 DATE: 25-Aug-06 Product Affected: CABGA-256 17x17mm, CVBGA-52/56 4.5X7.0mm, FPBGA-96 5.5x13.5mm, FPBGA-208 15x15mm, PBGA-119


    Original     		25-Aug-06 CABGA-256 17x17mm, CVBGA-52/56 FPBGA-96 FPBGA-208 15x15mm, PBGA-119 22x14mm, PBGA-272/416 sumitomo g760 sumitomo EME G760 SUMITOMO EME G770 IDT75N43102S50BCG KMC-3580 EME-G770 IDT75N414S125BC IDT70T653MS12BCG JESD22-B116 IDT75N43102S62BCG PDF

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description ICSSSTUAF32868A QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity


    Original     		28-BIT ICSSSTUAF32868A before284 199707558G PDF

    Untitled

    Abstract: No abstract text available
    Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description occurred on the open-drain QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity,


    Original     		28-BIT PDF