AD29
Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Text: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues
|
Original
|
V350EPC
i960Jx
401Gx
640-byte
64-byte
V350EPC
2348G
AD29
AD30
V350EPC-33
V350EPC-40
V960PBC
V961PBC
V96BMC
|
PDF
|
AD29
Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Text: V350EPC Rev. A0 / A1 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPC TM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues
|
Original
|
V350EPC
i960Jx
401Gx
640-byte
64-byte
V350EPC
2348G
AD29
AD30
V350EPC-33
V350EPC-40
V960PBC
V961PBC
V96BMC
|
PDF
|
ic960
Abstract: 54565
Text: Galileo-5 Benchmark Results 17 Jan 1997 Summary The following results are a summary of the detailed output of the benchmark tests below. All Benchmarks were performed with compiler optimization and with a standard 33Mhz I960jx Galileo-5 Board. Linpack-: 0.37 Mflops
|
Original
|
33Mhz
I960jx
ic960
80277634e-05
19209290e-07
38282776e-05
474366e-01
109734e-01
103098e
000000e
ic960
54565
|
PDF
|
js83
Abstract: 28f040 JS98 edo dram 72-pin simms 64mb JS108 JS-105 74LS373SC JS31-JS32 JS107 BYU25
Text: 32-bit i960Jx Galileo-5 Evaluation & Development Preliminary May 96, Rev. 1.0 System NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES • Flexible evaluation, benchmark, software, and hardware development system for the GT-32090 System
|
Original
|
32-bit
i960Jx
GT-32090
MON960)
i960Jx
33MHz
16MHz
66MHz
js83
28f040
JS98
edo dram 72-pin simms 64mb
JS108
JS-105
74LS373SC
JS31-JS32
JS107
BYU25
|
PDF
|
Untitled
Abstract: No abstract text available
Text: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MUTLTELEXED A/D PROCESSORS • Dual bi-directional address space remapping • Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification
|
Original
|
V961PBC
i960Jx,
PPC401Gx,
8/16-bit
i960Jx
PPC401Gx
16MHz
40MHz
|
PDF
|
CON20B
Abstract: 1N5005 CON28C hp simens GT-96010 MON960 10BASE PLCC28 GPP11 2d5 motorola capacitor pol
Text: alileo EV-96010 Evaluation Platform for the GT-96010 and Intel’s i960Jx CPU Preliminary Revision 1.0 7/24/97 www.galileoT.com info@galileoT.com Tel: +1-408.451.1400 Fax: +1-408.451.1404 EV-96010 - Evaluation Platform for the GT-96010 and Intel’s i960Jx CPU
|
Original
|
EV-96010
GT-96010
i960Jx
EV-96010
EV96010
CON20B
1N5005
CON28C
hp simens
MON960
10BASE PLCC28
GPP11
2d5 motorola
capacitor pol
|
PDF
|
GT-32090
Abstract: AD2699 PCMCIA SRAM Card MON960 QS3257 ad2690
Text: System Controller Galileo For i960JX Processors Technology, Inc. GT- 32090 Preliminary, Rev. 2.0 March 1996 NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES • Integrated system controller for embedded applications
|
Original
|
i960JX
16-33MHz
128MByte
256K-4M
32-bit
20MHz
25MHz
GT-32090
AD2699
PCMCIA SRAM Card
MON960
QS3257
ad2690
|
PDF
|
I960SX
Abstract: No abstract text available
Text: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues
|
Original
|
V350EPC
i960Jx
401Gx
640-byte
64-byte
8/16-bit
32-bit
16-bit
I960SX
|
PDF
|
AD14
Abstract: AD30 PPC401GF V292PBC V961PBC V961PBC-33 V961PBC-40 V96BMC V96SSC
Text: V961PBC Rev. B2 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface between Intel i960Jx, IBM PPC401Gx, processors and PCI bus • Dual bi-directional address space remapping • On-the-fly byte order endian conversion • Fully compliant with PCI 2.1 specification
|
Original
|
V961PBC
i960Jx,
PPC401Gx,
16MHz
40MHz
AD14
AD30
PPC401GF
V292PBC
V961PBC-33
V961PBC-40
V96BMC
V96SSC
|
PDF
|
I960SX
Abstract: V96SSC
Text: V96SSC Rev B1 HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Jx/Sx and PowerPC 401Gx PROCESSORS BLOCK DIAGRAM • Glueless interface between Intel’s i960Jx and i960Sx series processors, DRAM arrays, and peripheral devices Fast time-to-market • Support for boot PROM devices
|
Original
|
V96SSC
PowerPCTM401Gx
i960Jx
i960Sx
32-bit
33MHz
V96SSC,
2348G
|
PDF
|
24CO8
Abstract: a19t transistor 24co4 IC circuit diagram pin configurations of 24co4 1 24co4 S5933QE Sandy Bridge eeprom 24co2 24CO2 CSI 24C04
Text: A PPLIED M ICRO C IRCUITS C ORPORATION PCI PRODUCTS DATA BOOK For Marketing and Application Information Contact: Please refer to AMCC’s website at www.amcc.com for the latest Device Summary information for the S5920 and S5933 PCI products. Applied Micro Circuits Corporation
|
Original
|
S5920
S5933
24CO8
a19t transistor
24co4 IC circuit diagram
pin configurations of 24co4 1
24co4
S5933QE
Sandy Bridge
eeprom 24co2
24CO2
CSI 24C04
|
PDF
|
Untitled
Abstract: No abstract text available
Text: PCI 9060 December, 1995 PCI Bus Master Interface Chip for VERSION 1.2 Adapters and Embedded Systems Features • • • • • • • • General Description _
|
Original
|
PCI9060
9060-SIL-ER-P0-1
|
PDF
|
I960JX v363epc
Abstract: 160-Pin Flat Package pci bridge V380SDC
Text: V363EPC Data Sheet • • • • • • V363EPC Local Bus to PCI Bridge for Embedded Processors Device Highlights • Direct interface to these processors: • Up to 50 MHz on both PCI and local bus clocks • 3.3 V operation; 5 V tolerant input • Industrial temperature range
|
Original
|
V363EPC
160-pin
AM29030/40TM
401TM
I960JX v363epc
160-Pin Flat Package pci bridge
V380SDC
|
PDF
|
BT8233EHFB
Abstract: 5969b l8233
Text: R O C K W E L L Network access S E M I C O N D U C T O R Bt8233 ATM ServiceSAR with S Y S T E M S xBR Traffic Management datasheet PROVIDING HIGH SPEED MULTIMEDIA CONNECTIONS September 1998 Bt8233 ATM ServiceSAR with xBR Traffic Management The Bt8233 Service Segmentation and Reassembly Controller integrates in a single
|
Original
|
Bt8233
Bt8233
N8233DSB
BT8233EHFB
5969b
l8233
|
PDF
|
|
|
gvrp
Abstract: h140 motorola h654 wc H7C4 AC10 AD10 AE10 MDS212 MDS212CG st LD33
Text: MDS212 12-Port 10/100Mbps Ethernet Switch Data Sheet October 2003 Features • • • • • • • • • • 12 10/100Mbps Autosensing, Fast Ethernet ports with Reduced MII Interface 32-bit wide bi-directional pipe at 100Mhz provides 6.4Gbps pipe to connect two MDS212 chips
|
Original
|
MDS212
12-Port
10/100Mbps
10/100Mbps
32-bit
100Mhz
MDS212
gvrp
h140 motorola
h654 wc
H7C4
AC10
AD10
AE10
MDS212CG
st LD33
|
PDF
|
Untitled
Abstract: No abstract text available
Text: PCI 9030 Data Book PCI 9030 Data Book Version 1.1 January 2001 Website: http://www.plxtech.com Email: apps@plxtech.com Phone: 408 774-9060 800 759-3735 408 774-2169 Fax: 2001 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may
|
Original
|
9030-SIL-DB-Pam
Index-19
|
PDF
|
I960CA
Abstract: CRC10 RS8234 RS8250 on-demand multicast messages
Text: RS8234 ATM ServiceSAR Plus with xBR Traffic Management The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and
|
Original
|
RS8234
RS8234
28234-DSH-001-B
I960CA
CRC10
RS8250
on-demand multicast messages
|
PDF
|
Untitled
Abstract: No abstract text available
Text: - V 9 6 1 P B C Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS yi '« IC O * ’ • Glueless interface between i960Jx, PPC401Gx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t io n ™ architecture
|
OCR Scan
|
i960Jx,
PPC401Gx
576-byte
33MHz
16MHz
40MHz
|
PDF
|
LA3101
Abstract: PC19060 Igus LD-310 LDL8 pci9080 80960Cx 93C06 I960CX NM93CS06
Text: PCI 9060 T E C December, 1995 VERSION 1.2 PCI Bus Master Interface Chip for Adapters and Embedded Systems Features General D escrip tio n _ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local
|
OCR Scan
|
PCI9060
Q0007bl
xi6-31
Page-100-
0Q007b2
PCI90S0
LA3101
PC19060
Igus
LD-310
LDL8
pci9080
80960Cx
93C06
I960CX
NM93CS06
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ü ja lile o . GT-96010 Remote Access Coprocessor Preliminary Revision 1.0 8/12/97 Please contact Galileo Technology for possi b e updates before finalizing a design. FEATURES * Integrated serial communications controller and system core logic device - Direct interface to i960 Jx family of CPUs
|
OCR Scan
|
GT-96010
i960Hx
128Mbyte
256K-4M
32-bit
16-bit
31CLK
ive\9601Old
GT-96010
ve\960l
|
PDF
|
1010 817 g40
Abstract: GT-64111 I960JX
Text: GT-482xx liiii d | | |G O . GT-48212 / GT-48208 / GT-48207 Prelim inary Revision 1.2 D v 1/27/99 BaseX Please co n ta ct G alileo T echnology fo r possible u p dates b efore fin a lizin g a design. FEATURES • - - • - Provides packet switching functions between
|
OCR Scan
|
GT-482xx
GT-48212
GT-48208
GT-48207
256Kx32-bit
x16bit
1536-bytes
1010 817 g40
GT-64111
I960JX
|
PDF
|
Untitled
Abstract: No abstract text available
Text: .«artHEH » .¿•■■■I_ im ara« IM I 1 WIMIBII Galileo Technology, System Controller For ¡960JX Processors FEATURES Integrated system controller for embedded applica tions Supports the ¡960JX family of CPUs 16-33MHz bus frequency Flexible DRAM controller
|
OCR Scan
|
960JX
16-33MHz
128MByte
256K-4M
32-bit
20MHz
33MHz
GT-32090
|
PDF
|
Untitled
Abstract: No abstract text available
Text: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters
|
OCR Scan
|
9060SD
PCI9060SD
9060SD.
hflSS14^
|
PDF
|
Untitled
Abstract: No abstract text available
Text: PCI 9060 * E PCI Bus Master Interface Chip for Adapters and Embedded Systems December, 1995 VERSION 1.2 Features General Description_ • PCI Bus Master Interface supporting adapters and embedded systems • Two independent DMA channels for local bus
|
OCR Scan
|
PCI9060
100Version
00Q07
PCI9060
|
PDF
|