Untitled
Abstract: No abstract text available
Text: HM62A2016 Series Preliminary Dual 8,192-Word x 20-Bit Static Cache Memory • DESCRIPTION The HM62A2016 is a high speed 327,680-bit cache memory organized as two banks of 8,192 words by 20-bits. The device includes dual address latches, dual chip select latches, data multiplexer
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OCR Scan
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HM62A2016
192-Word
20-Bit
680-bit
20-bits.
62A2016
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PDF
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Untitled
Abstract: No abstract text available
Text: HM62A2016 Series- P relim inary Dual 8,192-Word x 20-Bit Static Cache Memory • DESCRIPTION The HM62A2016 is a high speed 327,680-bit cache memory organized as tw o banks of 8,192 words by 20-bits. The device includes dual address latches, dual chip select latches, data multiplexer
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OCR Scan
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HM62A2016
192-Word
20-Bit
680-bit
20-bits.
CP-52)
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PDF
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MIPS R3000
Abstract: MIPS R3000A
Text: HM62A2016 Series -P relim inary Dual 8,192-Word x 20-Bit Static Cache Memory • DESCRIPTIO N The H M 62A 2016 is a high speed 3 2 7 ,6 8 0 -b it cache m em ory organized as tw o banks o f 8,192 w ords by 20-bits. The device includes dual address latches, duai ch ip select latches, data m ultiplexer
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OCR Scan
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HM62A2016
192-Word
20-Bit
680-bit
20-bits.
select2A2016
MIPS R3000
MIPS R3000A
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PDF
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Untitled
Abstract: No abstract text available
Text: b lE ]> • 44clbECI3 OOPlbSO SbT ■ H I T S HM62A2016/2017 Series T - ^ 6 - 2 .3 - 1 2 - Dual 8192-word x 20-bit Static Cache Memory H IT A C H I/ LOGIC/ARRAYS/MEM The HM62A2016/2017 is a high speed 327680-bit cache memory organized as two banks of 8192
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OCR Scan
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44clbECI3
HM62A2016/2017
8192-word
20-bit
HM62A2016CP-17
HM62A2016CP-20
HM62A2016CP-25
HM62A2016CP-30
HM62A2017CP-17
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