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    HD74HC11 Price and Stock

    Texas Instruments CD74HC11M96

    Logic Gates Triple 3-Input
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Mouser Electronics CD74HC11M96 6,029
    • 1 $0.42
    • 10 $0.248
    • 100 $0.181
    • 1000 $0.165
    • 10000 $0.144
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    Texas Instruments SN74HC112N

    Flip Flops Dual
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Mouser Electronics SN74HC112N 3,594
    • 1 $0.78
    • 10 $0.548
    • 100 $0.435
    • 1000 $0.404
    • 10000 $0.352
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    Texas Instruments SN74HC11NSR

    Logic Gates Triple 3-Input Pos
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Mouser Electronics SN74HC11NSR 1,719
    • 1 $0.61
    • 10 $0.367
    • 100 $0.288
    • 1000 $0.26
    • 10000 $0.211
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    Texas Instruments CD74HC112NSR

    Flip Flops Hi-Sp CMOS Dual Neg J-K-Type Flip-Flop
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Mouser Electronics CD74HC112NSR 1,370
    • 1 $0.76
    • 10 $0.463
    • 100 $0.366
    • 1000 $0.332
    • 10000 $0.257
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    Texas Instruments CD74HC112E

    Flip Flops Dual Neg Edge Trig
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Mouser Electronics CD74HC112E 739
    • 1 $0.79
    • 10 $0.479
    • 100 $0.378
    • 1000 $0.343
    • 10000 $0.316
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    Find more HD74HC11 price and stock on Findchips.com

    HD74HC11 Datasheets (48)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    HD74HC11 Hitachi Semiconductor Triple 3-input AND Gates Original PDF
    HD74HC11 Renesas Technology Original PDF
    HD74HC11 Renesas Technology Triple 3-input AND Gates Original PDF
    HD74HC112 Hitachi Semiconductor Dual J-K Flip-Flops (with Preset and Clear) Original PDF
    HD74HC112 Renesas Technology Dual J-K Flip-Flops (with Preset and Clear) Original PDF
    HD74HC112AFP Renesas Technology Flip Flop, Dual J-K Flip-Flops (with Preset and Clear) Original PDF
    HD74HC112AP Renesas Technology Flip Flop, Dual J-K Flip-Flops (with Preset and Clear) Original PDF
    HD74HC112ARP Renesas Technology Flip Flop, Dual J-K Flip-Flops (with Preset and Clear) Original PDF
    HD74HC112AT Renesas Technology Flip Flop, Dual J-K Flip-Flops (with Preset and Clear) Original PDF
    HD74HC112FP Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 16-SOP Original PDF
    HD74HC112FP Renesas Technology Dual J-K Flip-Flops with Preset and Clear Original PDF
    HD74HC112FPEL Renesas Technology Dual J-K Flip-Flops (with Preset and Clear) Original PDF
    HD74HC112P Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 16-DIP Original PDF
    HD74HC112P Renesas Technology Dual J-K Flip-Flops (with Preset and Clear) Original PDF
    HD74HC112P Renesas Technology Dual J-K Flip-Flops with Preset and Clear Original PDF
    HD74HC112RP Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 16-SOP Original PDF
    HD74HC112RP Renesas Technology Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 16-SOP Original PDF
    HD74HC112T Hitachi Semiconductor Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 16-TSSOP Original PDF
    HD74HC112T Renesas Technology Flip-Flop, Negative-Edge, JK Flip-Flop, 2-Element, 2-Input, 16-TSSOP Original PDF
    HD74HC112T Renesas Technology Logic IC; Function: Dual J-K Flip-Flops with Preset and Clear; Package: TSSOP Original PDF

    HD74HC11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: HD74HC113 Dual J-K Flip-Flops with Preset REJ03D0563-0200 (Previous ADE-205-436) Rev.2.00 Oct 11, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and


    Original     		PDF HD74HC113 REJ03D0563-0200 ADE-205-436) HD74HC113P

    Hitachi DSA00279

    Abstract: No abstract text available
    Text: HD74HC11 Triple 3-input AND Gates Features • • • • • High Speed Operation: tpd = 9 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)


    Original     		PDF HD74HC11 Hitachi DSA00279

    Hitachi DSA00279

    Abstract: No abstract text available
    Text: HD74HC113 Dual J-K Flip-Flops with Preset Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is


    Original     		PDF HD74HC113 Hitachi DSA00279

    HD74HC11FPEL

    Abstract: HD74HC11 sem 2005 SOP14 package HD74HC11P HD74HC11RPEL PRDP0014AB-B PRSP0014DF-B
    Text: HD74HC11 Triple 3-input AND Gates REJ03D0539-0200 Previous ADE-205-411 Rev.2.00 Oct 06, 2005 Features • • • • • • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V


    Original     		PDF HD74HC11 REJ03D0539-0200 ADE-205-411) PRDP0014AB-B DP-14AV) HD74HC11P DILP-14 HD74HC11FPEL OP-14 HD74HC11RPEL HD74HC11FPEL HD74HC11 sem 2005 SOP14 package HD74HC11P HD74HC11RPEL PRDP0014AB-B PRSP0014DF-B

    HD74HC11

    Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN 2054.11
    Text: HD74HC11 Triple 3-input AND Gates ADE-205-411 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max


    Original     		PDF HD74HC11 ADE-205-411 HD74HC11 Hitachi DSA0095 DP-14 FP-14DA FP-14DN 2054.11

    HD74HC112

    Abstract: PRSP0016DH-B HD74HC112FPEL HD74HC112P PRDP0016AE-B
    Text: HD74HC112 Dual J-K Flip-Flops with Preset and Clear REJ03D0562-0200 (Previous ADE-205-435) Rev.2.00 Oct 11, 2005 Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of


    Original     		PDF HD74HC112 REJ03D0562-0200 ADE-205-435) HD74HC112 PRSP0016DH-B HD74HC112FPEL HD74HC112P PRDP0016AE-B

    Hitachi DSA00279

    Abstract: No abstract text available
    Text: HD74HC114 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each flip-flop has independent J, K and preset inputs and Q and Q outputs. Two flip-flops


    Original     		PDF HD74HC114 Hitachi DSA00279

    Hitachi DSA00279

    Abstract: No abstract text available
    Text: HD74HC112 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.


    Original     		PDF HD74HC112 Hitachi DSA00279

    FP-14DN

    Abstract: HD74HC113 DP-14 FP-14DA Hitachi DSA003765
    Text: HD74HC113 Dual J-K Flip-Flops with Preset Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is


    Original     		PDF HD74HC113 FP-14DN HD74HC113 DP-14 FP-14DA Hitachi DSA003765

    HD74HC112

    Abstract: Hitachi DSA003739
    Text: HD74HC112 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear


    Original     		PDF HD74HC112 HD74HC112 Hitachi DSA003739

    DP-14

    Abstract: FP-14DA FP-14DN HD74HC11 Hitachi DSA00333
    Text: HD74HC11 Triple 3-input AND Gates Features • • • • • High Speed Operation: tpd = 9 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)


    Original     		PDF HD74HC11 DP-14 FP-14DA FP-14DN HD74HC11 Hitachi DSA00333

    DP-14

    Abstract: FP-14DA FP-14DN HD74HC114 Hitachi DSA00334
    Text: HD74HC114 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each flip-flop has independent J, K and preset inputs and Q and Q outputs. Two flip-flops are


    Original     		PDF HD74HC114 DP-14 FP-14DA FP-14DN HD74HC114 Hitachi DSA00334

    Untitled

    Abstract: No abstract text available
    Text: HD74HC114 # Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock T h u flip-flop it edge sensitive to the clock input and change PIN ARRANGMENT state on the negative transition of the dock pulse. Each flipflop hai independant J, K, and preset inputs and Q and Q


    OCR Scan     		PDF HD74HC114

    74HC114

    Abstract: No abstract text available
    Text: HD74HC114 D u al J-K F lip -F lo p s with Preset, Common Clear, and Common Clock This flip-flop is edge sensitive to the clock input and change PIN ARRANGMENT state on the negative transition of the clock pulse. Each flipflop has independent J, K, and preset inputs and Q and Q


    OCR Scan     		PDF HD74HC114 74HC114

    Untitled

    Abstract: No abstract text available
    Text: HITACHI/ LOGIC/ARRAYS/NEM *Ì2~ " ¿ E l 4 4 ^ 3 0 3 □ □ l G 3 b [ì S 92D HD74HC112 # Dual J-K Flip-Flops Each flip -flo p has independent J, K , preset, clear, and clock 10369 T - % - D “7-07 w ith P re s e t and C le a r | PIN ARRANGEMENT inputs and Q and Q outputs. This device is edge sensitive to


    OCR Scan     		PDF HD74HC112 0D1D315 T-90-20

    Untitled

    Abstract: No abstract text available
    Text: HD74HC113 # Dual J-K Flip-Flops i-vith Preset • PIN ARRANGMENT This flip-flop ii edge sensitive to the dock input and change state on the negative going transition of the dock pulse. Each \~ J~ ~ one has independent v, K, dock, and preset inputs and Q -«nd


    OCR Scan     		PDF HD74HC113

    Untitled

    Abstract: No abstract text available
    Text: HITACHI/ LOGIC/ARRAYS/MEd ^5 T>Ë| i t i n t 2 0 3 0Q10330 Q 92D HD74HC11 # 103 30 D TVV 3 ' 2 / Triple 3-input AND Gates • F E A T UR E S I PIN ARRANGEMENT • High Speed Operation: tpcj= 9ns typ. C/_=50pF • High O u tptt Current: Fanout of 10 LSTTL Loads


    OCR Scan     		PDF 0Q10330 HD74HC11 0D1D315 T-90-20

    Untitled

    Abstract: No abstract text available
    Text: HITACHI/ LOGIC/AR RAYS/MEM =IS DË1 4 ln t a 0 3 0010371 3 | 92D HD74HC113 10371 D T -q o -O”7 -07 Dual J-K Flip-Flops (with Preset This flip-flop is edge sensitive to the clock input end change | PIN ARRANGMENT state on the negative going transition of the clock pulse. Each


    OCR Scan     		PDF HD74HC113

    Untitled

    Abstract: No abstract text available
    Text: HD74HC112 • Dual J K Flip-Flops with P reset and Clear Each flip-flop has independent J, K, preset, clear, and clock • PIN ARRANGEMENT input» and Q and Q outputs. This device is edge sensitive to the d o c k input and change state on the negative going transi­


    OCR Scan     		PDF HD74HC112 Ta-25

    Untitled

    Abstract: No abstract text available
    Text: HD74HC112 Each flip -flo p has independent J, K, # Dual J-K Flip-Flops w ith P re s e t and C le a r preset, clear, and clock | PIN ARRANGEMENT inputs and Q and Q outputs. This device is edge sensitive to the clock in put and change state on the negative going transi­


    OCR Scan     		PDF HD74HC112

    Untitled

    Abstract: No abstract text available
    Text: HD74HC11 # Triple 3-input AND Gates I PIN A R R A N G EM EN T • FEATURES • Hiflri Speed Operation: tp<j m 9ns typ. Q_ “ 5 0 p F I • Higii O utp ut C u rre n t: Fanout o f 10 L S T T L Load* • Wide Operating Voltage: V c c « 2 ~ 6 V • L o w Inp u t Current: 1 p A max.


    OCR Scan     		PDF HD74HC11 To-25

    Untitled

    Abstract: No abstract text available
    Text: HD74HC11 # Triple 3-input AND Gates • FEATURES I PIN ARRANGEMENT • High Speed Operation: tpcj = 9ns ty p . C/_ = 5 0 p F • High O u tp u t C urrent: Fanout o f 10 L S T T L Loads • Wide Operating Voltage: Vcc = 2 ~ 6 V • Low In p u t C urrent: 1/uA max.


    OCR Scan     		PDF HD74HC11 20jjA

    HC125

    Abstract: HC126 HD74HC128 HC-126 HD74HC1125 HD74HC126
    Text: HD74HC1125, HD74HC12 6 * S Ä Ä * The HD74HC125, HD74HC128 faquir* the 3-«ta«e control input C to be taken high to put the output into the high Im­ pedance condition, whereat the HD74HC125, HD74HC126 requires the control input to be low to put the output into


    OCR Scan     		PDF HD74HC1125, HD74HC12 HD74HC125, HD74HC128 HD74HC126 HC125 HC126 HC125 HC126 HC-126 HD74HC1125

    Untitled

    Abstract: No abstract text available
    Text: HD74HC11 # Triple 3 -input AND Gates PIN ARRANGEMENT • FEATURES • • • • • High Speed Operation: tpdm9ns typ. C/_ *50pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: Vcc = 2 ~ 6 V Low Input Current: 1/uA max. Low Quiescent Supply Current:/cc (static) = 1>iA max. (7a> 25°C)


    OCR Scan     		PDF HD74HC11