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    EP195 Search Results

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    EP195 Price and Stock

    Rochester Electronics LLC MC10EP195FAR2

    ACTIVE DELAY LINE, PROGRAMMABLE
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    DigiKey MC10EP195FAR2 Bulk 6,262 49
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    Rochester Electronics LLC MC10EP195FA

    ACTIVE DELAY LINE, PROGRAMMABLE
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    DigiKey MC10EP195FA Tray 3,700 49
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    onsemi MC100EP195FAR2G

    IC DELAY LN 1024TAP PROG 32LQFP
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    DigiKey MC100EP195FAR2G Cut Tape 2,996 1
    • 1 $21.21
    • 10 $19.493
    • 100 $16.4628
    • 1000 $14.64486
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    MC100EP195FAR2G Digi-Reel 2,996 1
    • 1 $21.21
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    Avnet Americas MC100EP195FAR2G Reel 4 Weeks 23
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    • 100 $15.428
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    Mouser Electronics MC100EP195FAR2G 1,801
    • 1 $21.21
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    Newark MC100EP195FAR2G Reel 2,000
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    Rochester Electronics MC100EP195FAR2G 9,135 1
    • 1 $16.08
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    Avnet Silica MC100EP195FAR2G 31 Weeks 2,000
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    Chip1Stop MC100EP195FAR2G 119
    • 1 $63.5
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    Rochester Electronics LLC MC10EP195FAG

    ACTIVE DELAY LINE, PROGRAMMABLE,
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    DigiKey MC10EP195FAG Bulk 2,559 28
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    Rochester Electronics LLC MC100EP195FA

    ACTIVE DELAY LINE, PROGRAMMABLE
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey MC100EP195FA Tray 2,012 49
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    • 100 $6.14
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    EP195 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    PS2360

    Abstract: No abstract text available
    Text: MC100EP196 3.3VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further


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    PDF MC100EP196 EP195 EP196 r14525 MC100EP196/D PS2360

    Untitled

    Abstract: No abstract text available
    Text: MC100EP196A 3.3 V ECL Programmable Delay Chip With FTUNE The MC100EP196A is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further


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    PDF MC100EP196A MC100EP196A EP195 EP196A MC100EP196A/D

    PS-4480 B

    Abstract: E196 MC100 MC100EP196 ps 5040 750MV
    Text: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in


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    PDF MC100EP196 MC100EP196 EP195 EP196 MC100EP196/D PS-4480 B E196 MC100 ps 5040 750MV

    PS-4480 B

    Abstract: ic 4440 circuit diagram E196 MC100 MC100EP196
    Text: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in


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    PDF MC100EP196 MC100EP196 EP195 EP196 MC100EP196/D PS-4480 B ic 4440 circuit diagram E196 MC100

    PS-4480 B

    Abstract: No abstract text available
    Text: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in


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    PDF MC100EP196 EP195 EP196 MC100EP196/D PS-4480 B

    PS-4480 B

    Abstract: PS-4480
    Text: MC100EP196 3.3VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further


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    PDF MC100EP196 EP195 EP196 r14525 MC100EP196/D PS-4480 B PS-4480

    PS-4480

    Abstract: MC100 MC100EP196 MC100EP196FA MC100EP196FAR2
    Text: MC100EP196 3.3VĄECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further


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    PDF MC100EP196 MC100EP196 EP195 EP196 r14525 MC100EP196/D PS-4480 MC100 MC100EP196FA MC100EP196FAR2

    ps5120

    Abstract: No abstract text available
    Text: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in


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    PDF MC100EP196 EP195 EP196 BRD8011/D. MC100EP196 AN1405/D AN1406/D AN1503/D AN1504/D ps5120

    E196

    Abstract: MC100 MC100EP196
    Text: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tuneability in


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    PDF MC100EP196 MC100EP196 EP195 EP196 MC100EP196/D E196 MC100

    Untitled

    Abstract: No abstract text available
    Text: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar


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    PDF MC100EP196B MC100EP196B EP195 EP196B MC100EP196B/D

    Untitled

    Abstract: No abstract text available
    Text: EP195B 3.3V ECL Programmable Delay Chip Descriptions The EP195B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and


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    PDF MC100EP195B MC100EP195B EP195B MC100EP195B/D

    Untitled

    Abstract: No abstract text available
    Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the


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    PDF MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10E196/D

    Untitled

    Abstract: No abstract text available
    Text: EP195, EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and


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    PDF MC10EP195, MC100EP195 MC10/100EP195 EP195 r14525 MC10EP195/D

    VCF12

    Abstract: LQFP-32 MC100 QFN32 QFN-32
    Text: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar


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    PDF MC100EP196B MC100EP196B EP195 EP196B MC100EP196B/D VCF12 LQFP-32 MC100 QFN32 QFN-32

    MC100EP195

    Abstract: QFN-32 footprint MC10EP195 QFN32 7850 AE
    Text: EP195, EP195 3.3V ECL Programmable Delay Chip The MC10/EP195 is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. http://onsemi.com


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    PDF MC10EP195, MC100EP195 MC10/100EP195 EP195 MC10EP195/D MC100EP195 QFN-32 footprint MC10EP195 QFN32 7850 AE

    MC100EP195

    Abstract: MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2
    Text: EP195, EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and


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    PDF MC10EP195, MC100EP195 MC10/100EP195 EP195 r14525 MC10EP195/D MC100EP195 MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2

    ic 4440 circuit diagram

    Abstract: pin diagram of ic 4440 QFN-32 footprint MC100 QFN32 LQFP-32 footprint
    Text: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar


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    PDF MC100EP196B MC100EP196B EP195 EP196B MC100EP196B/D ic 4440 circuit diagram pin diagram of ic 4440 QFN-32 footprint MC100 QFN32 LQFP-32 footprint

    k1117

    Abstract: R36W power transistor k1821 L46R k1518 k1117 transistor k2225 transistor k2225 k1317 transistor k1317
    Text: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by: Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Schematic Information The kit contains representative input and output schematics, netlists, and waveform used for the ECLinPS


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    PDF AND8009/D k1117 R36W power transistor k1821 L46R k1518 k1117 transistor k2225 transistor k2225 k1317 transistor k1317

    KLT20

    Abstract: k1648 klt22 KEL32 MC100 HEP64 KLT21 LP17 KEP32 HEP139
    Text: AND8002/D ECLinPS, ECLinPS Lite, ECLinPS Plus, ECLinPS MAX, and GigaComm Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and


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    PDF AND8002/D KLT20 k1648 klt22 KEL32 MC100 HEP64 KLT21 LP17 KEP32 HEP139

    motorola HEP cross reference

    Abstract: EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64
    Text: BR1513/D Rev. 2, Apr-2001 ECLinPS Plus Device Data ECLinPS Plus Device Data Advanced ECL in Picoseconds BR1513/D Rev. 2, Apr–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved” ECLinPS, ECLinPS Lite, and ECLinPS Plus are trademarks of Semiconductor Components Industries, LLC.


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    PDF BR1513/D Apr-2001 r14525 DLD601 motorola HEP cross reference EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64

    Untitled

    Abstract: No abstract text available
    Text: MC100EP196 3.3V ECL Programmable Delay Chip with FTUNE The MC100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar


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    PDF MC100EP196 MC100EP196 EP195 EP196 MC100EP196/D

    R36W

    Abstract: k1420 N52C N38C l46r k0114 N53C transistor k1117 k2225 transistor transistors k2628
    Text: AND8009/D ECLinPS Plus SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Broadband Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information


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    PDF AND8009/D r14525 AND8009/D R36W k1420 N52C N38C l46r k0114 N53C transistor k1117 k2225 transistor transistors k2628

    ic 4440 circuit diagram

    Abstract: MC100EP195 MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2
    Text: EP195, EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and


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    PDF MC10EP195, MC100EP195 MC10/100EP195 EP195 r14525 MC10EP195/D ic 4440 circuit diagram MC100EP195 MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2

    MC100EP196

    Abstract: MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FA MC10EP196FAR2
    Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the


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    PDF MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10EP196/D MC100EP196 MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FA MC10EP196FAR2