sab audio
Abstract: No abstract text available
Text: 74ACT11646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS061A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • • • DW PACKAGE TOP VIEW Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes
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Original
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74ACT11646
SCAS061A
D2957,
500-mA
sab audio
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PDF
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54ACT11521
Abstract: 74ACT11521 D2957
Text: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS SCAS023A – D2957, JULY 1978 – REVISED APRIL 1993 • • • • • • • Compares Two 8-Bit Words Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations
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Original
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54ACT11521,
74ACT11521
SCAS023A
D2957,
500-mA
300-mil
54ACT11521
54ACT11521
74ACT11521
D2957
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 74ACT11623 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS059A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • • • • DW OR NT PACKAGE TOP VIEW Local Bus-Latch Capability Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes
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Original
|
74ACT11623
SCAS059A
D2957,
500-mA
300-mil
|
PDF
|
74AC11533
Abstract: No abstract text available
Text: 54AC11533, 74AC11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS ą SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • • • 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE 8-Latches in a Single Package
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Original
|
54AC11533,
74AC11533
54AC11533
74AC11533
SCAS004
D2957,
500-mA
300-mil
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54ACT11533, 74ACT11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS ą SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • • • • Eight Latches in a Single Package 3-State Bus-Driving Inverting Outputs Full Parallel Access for Loading
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Original
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54ACT11533,
74ACT11533
54ACT11533
74ACT11533
SCAS017A
D2957,
500-mA
300-mil
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW
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OCR Scan
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54AC11109,
74AC11109
TI0066--
D2957,
500-mA
STD-883C
300-mil
54AC11109
74AC11109
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PDF
|
Untitled
Abstract: No abstract text available
Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to
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OCR Scan
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54AC11032,
74AC11032
TI0060--
D2957,
500-mA
300-mil
54AC11032
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PDF
|
Untitled
Abstract: No abstract text available
Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations
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OCR Scan
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54AC11021
74AC11021
D2957.
500-mA
300-mll
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise
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OCR Scan
|
54AC11002,
74AC11002
D2957,
500-mA
300-mil
54AC11002
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS S C A S Q 2 3 A - D2957, JU L Y 1978- R E V IS E D A P R I L 1993 54ACT11521 . . . J P A C K A G E 74ACT11521 . . . OB, D W O R N P A C K A G E i * Compares Two 8-Bit Words * Inputs Are TTL-Voltage Compatible
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OCR Scan
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54ACT11521,
74ACT11521
D2957,
54ACT11521
74ACT11521
500-mA
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise
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OCR Scan
|
54ACT11002
74ACT11002
SCAS003A
D2957,
500-mA
300-mll
|
PDF
|
1sv 134
Abstract: No abstract text available
Text: 54ACT11640, 74ACT11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS027A - D2957, JULY 1987 - REVISED APRIL 1993 54ACT11640. . . JT PACKAGE 74ACT11640 . . . DW OR NT PACKAGE TOP VIEW B idirectional Bus Transceivers In H ig h-D ensity 24-P in Packages
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OCR Scan
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54ACT11640,
74ACT11640
SCAS027A
D2957,
500-m
300-m
54ACT11640.
74ACT11640
1sv 134
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PDF
|
D2957
Abstract: No abstract text available
Text: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations
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OCR Scan
|
500-mA
300-mll
AC11240
AC11244,
D2957
|
PDF
|
74AC11520
Abstract: No abstract text available
Text: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations
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OCR Scan
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54AC11520
74AC11520
D2957,
500-mA
300-mil
54AC11520
74AC11S20.
|
PDF
|
|
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tl401
Abstract: No abstract text available
Text: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCAS046 - D2957. DECEMBER 1986 - REVISED APRIL 1993 54ACT11074. . . J PACKAGE 74ACT11074. . . D OR N PACKAGE * Inputs Are TTL-Voltage Compatible
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OCR Scan
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54ACT11074,
74ACT11074
SCAS046
D2957.
500-mA
300-mil
tl401
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54ACT11241, 74ACT11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T I0073— D2957 JULY 1987— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54A C T 11241 . . . J T P ACKA G E 74A C T11 2 41 . . . D W OH N T P ACKA G E • 3-State Outputs Drive Bus Lines or Buffer
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OCR Scan
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54ACT11241,
74ACT11241
I0073--
D2957
500-mA
300-mil
|
PDF
|
74AC11533
Abstract: 123D20
Text: *»4AP11*511 744011*511 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0085— D2957, JULY 1987— REVISED JAN U AR Y 1990 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE • 8-Latches in a Single Package • 3-State Bus-Driving Inverting Outputs
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OCR Scan
|
4AP11
TI0085--
D2957,
500-mA
300-mil
54AC11533
74AC11533
74AC11533
123D20
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PDF
|
TI009
Abstract: No abstract text available
Text: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to
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OCR Scan
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54AC11643,
I0095--
D2957,
500-mA
300-mil
54AC11643
74AC11643
TI009
|
PDF
|
D2957
Abstract: 1987-REVISEDAPRIL
Text: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted
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OCR Scan
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54ACT11030
74ACT11030
D2957.
1987-REVISEDAPRIL
500-mA
300-mll
D2957,
D2957
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PDF
|
ti0041
Abstract: No abstract text available
Text: 54ACT11000, 74ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES T I0041— D2957, JUNE 1967— REVISED M ARCH 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 11 0 00 . . . J P ACKA G E 7 4 A C T 1 1000 . . . D O R N PACKA GE • Flow-Through Architecture to Optimize PCB
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OCR Scan
|
54ACT11000,
74ACT11000
I0041--
D2957,
500-mA
300-mil
ti0041
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54AC11074,74AC11074 DUAL D-TYPE POSUIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, D E C E M B E R 1986 - REVISED A P R IL 1983 54AC11074. . . J PACKAGE 74AC11074. . . D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout
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OCR Scan
|
54AC11074
74AC11074
D2957,
500-mA
300-mil
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54AC11020,74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES D2957, MAHCH 1987-REVISEDAPRIL1993 54AC11020. . . J PACKAGE 74AC11020. . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise
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OCR Scan
|
54AC11020
74AC11020
D2957,
1987-REVISEDAPRIL1993
500-mA
300-mil
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957. JUNE 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Pertormance Implanted CMOS 1-^m Process
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OCR Scan
|
54AC11030,
74AC11030
D2957.
1987-R
500-mA
300-mll
S4AC11032-85
54AC11030
D2957,
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 54AC11027, 74AC11027 TRIPLE 3-INPUT POSITIVE-NOR GATES TI0056— D2957, JULY 1987—REVISED MARCH 1990 54AC11027 . . . J PACKAGE 74AC11027 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pln V c c and GND Configurations to
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OCR Scan
|
54AC11027,
74AC11027
TI0056--
D2957,
1987--REVISED
500-mA
300-mil
54AC11027
74AC11027
|
PDF
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