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CY7C2544KV18 Price and Stock

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Infineon Technologies AG CY7C2544KV18-333BZI IC SRAM 72MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C2544KV18-333BZI	Tray			136	1 - 10 - 100 - 1000 $222.925 10000 $222.925	Buy Now
Rochester Electronics LLC CY7C2544KV18-300BZI IC SRAM 72MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C2544KV18-300BZI	Tray			2	1 - 10 $253.67 100 $253.67 1000 $253.67 10000 $253.67	Buy Now
Infineon Technologies AG CY7C2544KV18-300BZI IC SRAM 72MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C2544KV18-300BZI	Tray			136	1 - 10 - 100 - 1000 $219.525 10000 $219.525	Buy Now
Cypress Semiconductor CY7C2544KV18-300BZI QDR SRAM, 2MX36, 0.45ns PBGA165 '
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Rochester Electronics	CY7C2544KV18-300BZI		78		1	1 $243.91 10 $243.91 100 $229.28 1000 $207.32 10000 $207.32	Buy Now

CY7C2544KV18 Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C2544KV18-300BZI		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 300MHZ 165FBGA		Original	PDF
CY7C2544KV18-333BZI		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 72MBIT 333MHZ 165FBGA		Original	PDF

CY7C2544KV18 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CY7C2544KV18-300BZI Abstract: No abstract text available Text: CY7C2540KV18, CY7C2555KV18 CY7C2542KV18, CY7C2544KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:	Original	CY7C2540KV18, CY7C2555KV18 CY7C2542KV18, CY7C2544KV18 72-Mbit CY7C2540KV18 CY7C2555KV18 CY7C2542KV18 CY7C2544KV18-300BZI	PDF
CY7C2544KV18-300BZI Abstract: CY7C2544KV18 Text: CY7C2540KV18, CY7C2555KV18 CY7C2542KV18, CY7C2544KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:	Original	CY7C2540KV18, CY7C2555KV18 CY7C2542KV18, CY7C2544KV18 72-Mbit CY7C2542KV18 CY7C2544KV18-300BZI CY7C2544KV18	PDF
CY7C25442KV18 Abstract: CY7C25442KV18-300BZI 78 ball fbga thermal resistance 3M Touch Systems Text: CY7C25442KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency	Original	CY7C25442KV18 72-Mbit CY7C25442KV18 CY7C25442KV18-300BZI 78 ball fbga thermal resistance 3M Touch Systems	PDF
Untitled Abstract: No abstract text available Text: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions	Original	CY7C25442KV18 72-Mbit	PDF
neutron Abstract: 3M Touch Systems Text: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions	Original	CY7C25442KV18 72-Mbit neutron 3M Touch Systems	PDF
Untitled Abstract: No abstract text available Text: CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports ❐ Supports concurrent transactions	Original	CY7C25442KV18 72-Mbit 333-MHz	PDF
3M Touch Systems Abstract: No abstract text available Text: CY7C25402KV18, CY7C25552KV18 CY7C25422KV18, CY7C25442KV18 72-Mbit QDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency with ODT Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:	Original	CY7C25402KV18, CY7C25552KV18 CY7C25422KV18, CY7C25442KV18 72-Mbit CY7C25402KV18 CY7C25552KV18 CY7C25422KV18 3M Touch Systems	PDF