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    CY7C151 Price and Stock

    Flip Electronics CY7C1515KV18-250BZI

    IC SRAM 72MBIT PAR 165FBGA
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    DigiKey CY7C1515KV18-250BZI Tray 1,420 10
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    Flip Electronics CY7C1518KV18-300BZXI

    IC SRAM 72MBIT PARALLEL 165FBGA
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    DigiKey CY7C1518KV18-300BZXI Tray 1,304 5
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    Flip Electronics CY7C1515KV18-250BZXI

    IC SRAM 72MBIT PAR 165FBGA
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    DigiKey CY7C1515KV18-250BZXI Tray 1,203 5
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    Flip Electronics CY7C1515KV18-250BZXC

    IC SRAM 72MBIT PAR 165FBGA
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    DigiKey CY7C1515KV18-250BZXC Tray 855 5
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    Flip Electronics CY7C1518KV18-250BZI

    IC SRAM 72MBIT PAR 165FBGA
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    DigiKey CY7C1518KV18-250BZI Bulk 852 5
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    • 10 $109.79
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    Find more CY7C151 price and stock on Findchips.com

    CY7C151 Datasheets (302)

    Part ECAD Model Manufacturer Description Curated Type PDF
    CY7C1510AV18 Cypress Semiconductor 72-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1510AV18 Cypress Semiconductor 72-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1510AV18 Cypress Semiconductor 72-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1510JV18 Cypress Semiconductor 72-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1510V18 Cypress Semiconductor 72-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1511AV18 Cypress Semiconductor 72-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1511V18 Cypress Semiconductor 72-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1511V18-167BZC Cypress Semiconductor 72 Mbit QDR-II SRAM 4-word burst architecture. Speed 167 MHz. Original PDF
    CY7C1511V18-200BZC Cypress Semiconductor 72 Mbit QDR-II SRAM 4-word burst architecture. Speed 200 MHz. Original PDF
    CY7C1511V18-250BZC Cypress Semiconductor 72 Mbit QDR-II SRAM 4-word burst architecture. Speed 250 MHz. Original PDF
    CY7C1512 Cypress Semiconductor 64K x 8 Static RAM Original PDF
    CY7C1512-15SC Cypress Semiconductor 64K x 8 Static RAM Original PDF
    CY7C1512-15SC Cypress Semiconductor 64K x 8 Static RAM Original PDF
    CY7C1512-15SC Cypress Semiconductor 64K x 8 Static RAM Scan PDF
    CY7C1512-15SC Cypress Semiconductor 64K x 8 Static RAM Scan PDF
    CY7C1512-15VC Cypress Semiconductor 64K x 8 Static RAM Scan PDF
    CY7C1512-15ZC Cypress Semiconductor 64K x 8 Static RAM Original PDF
    CY7C1512-15ZC Cypress Semiconductor 64K x 8 Static RAM Original PDF
    CY7C1512-15ZC Cypress Semiconductor 64K x 8 Static RAM Scan PDF
    CY7C1512-15ZI Cypress Semiconductor SRAM GP Single Port Original PDF
    ...

    CY7C151 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1518KV18, CY7C1520KV18 72-Mbit DDR II SRAM Two-Word Burst Architecture 72-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18, 2 M × 36 CY7C1518KV18 – 4 M × 18 ■ 333 MHz clock for high bandwidth CY7C1520KV18 – 2 M × 36


    Original     		PDF CY7C1518KV18, CY7C1520KV18 72-Mbit CY7C1518KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 兆2-Mb典t唯Q当R 唯存存唯止RAM唯2唯 • ■ J正AG唯114版.1唯 ■ 唯样PLL核 ❐ ■ 350唯M字争唯 唯2唯 ■ ■ 唯样当当R核唯 唯 唯兆00唯M字争唯 K唯 ■ ❐ 唯K 唯350 M字争


    Original     		PDF CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 1510Kæ 1512Kæ 1514Kæ 1525Kæ

    CY7C1510AV18

    Abstract: CY7C1512AV18 CY7C1514AV18 CY7C1525AV18 CY7C1512AV18-167BZXC
    Text: CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1510AV18 – 8M x 8 ■ 250 MHz clock for high bandwidth


    Original     		PDF CY7C1510AV18, CY7C1525AV18 CY7C1512AV18, CY7C1514AV18 72-Mbit CY7C1510AV18 CY7C1512AV18 CY7C1510AV18 CY7C1512AV18 CY7C1514AV18 CY7C1525AV18 CY7C1512AV18-167BZXC

    CY7C1520V18-200BZXC

    Abstract: CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18
    Text: CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		PDF CY7C1516V18, CY7C1527V18 CY7C1518V18, CY7C1520V18 72-Mbit CY7C1520V18-200BZXC CY7C1520V18-300BZC CY7C1518V18-300BZC CY7C1516V18 CY7C1518V18 CY7C1520V18 CY7C1527V18

    CY7C1512V18-250BZXC

    Abstract: CY7C1510V18 CY7C1512V18 CY7C1514V18 CY7C1525V18
    Text: CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth


    Original     		PDF CY7C1510V18, CY7C1525V18 CY7C1512V18, CY7C1514V18 72-Mbit CY7C1512V18-250BZXC CY7C1510V18 CY7C1512V18 CY7C1514V18 CY7C1525V18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 72-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1511KV18 – 8M x 8 ■ 333 MHz clock for high bandwidth


    Original     		PDF 72-Mbit CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 CY7C1511KV18 CY7C1526KV18 CY7C1513KV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 72-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1511KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth


    Original     		PDF 72-Mbit CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 CY7C1511KV18 CY7C1526KV18 CY7C1513KV18

    CY7C1515JV18-167BZI

    Abstract: No abstract text available
    Text: CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1511JV18 – 8M x 8 ■ 300 MHz clock for high bandwidth


    Original     		PDF CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit CY7C1511JV18 CY7C1526JV18 CY7C1513JV18 CY7C1515JV18-167BZI

    350bz

    Abstract: No abstract text available
    Text: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 350 MHz Clock for High Bandwidth


    Original     		PDF 72-Mbit CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 350bz

    Untitled

    Abstract: No abstract text available
    Text: CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 72-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 267 MHz Clock for High Bandwidth ■


    Original     		PDF CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 72-Mbit CY7C1510JV18 CY7C1525JV18 CY7C1512JV18

    CY7C1516JV18

    Abstract: CY7C1518JV18 CY7C1520JV18 CY7C1527JV18
    Text: CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		PDF CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 72-Mbit CY7C1516JV18 CY7C1518JV18 CY7C1520JV18 CY7C1527JV18

    CY7C1511AV18

    Abstract: CY7C1513AV18 CY7C1515AV18 CY7C1526AV18
    Text: CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 72-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original     		PDF CY7C1511AV18, CY7C1526AV18 CY7C1513AV18, CY7C1515AV18 72-Mbit CY7C1511AV18 CY7C1513AV18 CY7C1511AV18 CY7C1513AV18 CY7C1515AV18 CY7C1526AV18

    CY7C1517V18

    Abstract: CY7C1519V18 CY7C1521V18 CY7C1528V18
    Text: CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18 72-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency


    Original     		PDF CY7C1517V18 CY7C1528V18 CY7C1519V18 CY7C1521V18 72-Mbit 300-MHz CY7C1517V18 CY7C1519V18 CY7C1521V18 CY7C1528V18

    CY7C1513KV18-200BZXC

    Abstract: No abstract text available
    Text: CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 72-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1511KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth


    Original     		PDF CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 72-Mbit CY7C1511KV18 CY7C1513KV18 CY7C1513KV18-200BZXC

    CY7C1510V18

    Abstract: CY7C1512V18 CY7C1514V18
    Text: CY7C1512V18 CY7C1514V18 72 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for High Bandwidth ■ 2 word burst on all accesses


    Original     		PDF CY7C1512V18 CY7C1514V18 CY7C1510V18 CY7C1512V18 CY7C1514V18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1518KV18 CY7C1520KV18 72-Mbit DDR II SRAM Two-Word Burst Architecture 72-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18, 2 M × 36 CY7C1518KV18 – 4 M × 18 ■ 333 MHz clock for high bandwidth CY7C1520KV18 – 2 M × 36


    Original     		PDF CY7C1518KV18 CY7C1520KV18 72-Mbit

    CY7C1512KV18-250BZXI

    Abstract: No abstract text available
    Text: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture 72-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF 72-Mbit CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1512KV18-250BZXI

    Untitled

    Abstract: No abstract text available
    Text: CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1525KV18 – 8 M x 9


    Original     		PDF CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit CY7C1525KV18 CY7C1512KV18

    CY7C1512KV18-250BZXC

    Abstract: CY7C1512KV18-250BZC CY7C1525KV18-250BZXC MO-216
    Text: CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1510KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth


    Original     		PDF 72-Mbit CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 CY7C1510KV18 CY7C1525KV18 CY7C1512KV18 CY7C1512KV18-250BZXC CY7C1512KV18-250BZC CY7C1525KV18-250BZXC MO-216

    7C15121

    Abstract: CY7C1512-25SC CY7C1512 CY7C1512-15SC CY7C1512-15ZC CY7C1512-20SC CY7C1512-20ZI
    Text: 1CY 7C15 12 PRELIMINARY CY7C1512 64K x 8 Static RAM Features • High speed — tAA = 15 ns • CMOS for optimum speed/power • Low active power — 770 mW • Low standby power — 28 mW • Automatic power-down when deselected • TTL-compatible inputs and outputs


    Original     		PDF CY7C1512 CY7C1512 7C15121 CY7C1512-25SC CY7C1512-15SC CY7C1512-15ZC CY7C1512-20SC CY7C1512-20ZI

    M/288M-

    Abstract: No abstract text available
    Text: CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 72-Mbit QDR - II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 300-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original     		PDF CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 72-Mbit 300-MHz Selects278-MHz M/288M-

    Untitled

    Abstract: No abstract text available
    Text: CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 72-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1511KV18 – 8M x 8 ■ 333 MHz clock for high bandwidth


    Original     		PDF 72-Mbit CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 CY7C1511KV18 CY7C1526KV18 CY7C1513KV18

    CY7C1520JV18

    Abstract: CY7C1516JV18 CY7C1518JV18 CY7C1527JV18 tms 1035
    Text: CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		PDF CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 72-Mbit CY7C1520JV18 CY7C1516JV18 CY7C1518JV18 CY7C1527JV18 tms 1035

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY7C1512 64K x 8 Static RAM Features and three-state drivers. This device has an automatic pow­ er-down feature that reduces power consumption by more than 75% when deselected. • High speed — tAA = 15ns Writing to the device is accomplished by taking chip enable


    OCR Scan     		PDF CY7C1512