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    CY7C1314CV18 Search Results

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    CY7C1314CV18 Price and Stock

    Rochester Electronics LLC CY7C1314CV18-167BZC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1314CV18-167BZC Tray 412 10
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    Rochester Electronics LLC CY7C1314CV18-250BZC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1314CV18-250BZC Tray 154 9
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    Rochester Electronics LLC CY7C1314CV18-200BZI

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1314CV18-200BZI Tray 72 9
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    Rochester Electronics LLC CY7C1314CV18-200BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1314CV18-200BZC Tray 43 10
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    • 10 $31.96
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    Infineon Technologies AG CY7C1314CV18-200BZI

    IC SRAM 18MBIT PARALLEL 165FBGA
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    Avnet Americas CY7C1314CV18-200BZI Tray 4 Weeks 11
    • 1 $33.85
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    CY7C1314CV18 Datasheets (9)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1314CV18 Cypress Semiconductor 18-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1314CV18-167BZC Cypress Semiconductor 18-Mbit QDR -II SRAM 2-Word Burst Architecture Original PDF
    CY7C1314CV18-167BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 167MHZ 165FBGA Original PDF
    CY7C1314CV18-200BZC Cypress Semiconductor 18-Mbit QDR -II SRAM 2-Word Burst Architecture Original PDF
    CY7C1314CV18-200BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 200MHZ 165FBGA Original PDF
    CY7C1314CV18-200BZI Cypress Semiconductor 18-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V Original PDF
    CY7C1314CV18-200BZI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 200MHZ 165FBGA Original PDF
    CY7C1314CV18-250BZC Cypress Semiconductor 18-Mbit QDR -II SRAM 2-Word Burst Architecture Original PDF
    CY7C1314CV18-250BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 250MHZ 165FBGA Original PDF

    CY7C1314CV18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth


    Original
    PDF CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 18-Mbit 250-MHz

    CY7C1314CV18

    Abstract: CY7C1310CV18 CY7C1312CV18 CY7C1910CV18 CY7C1314CV18-250BZXC
    Text: CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■


    Original
    PDF CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit CY7C1310CV18 CY7C1312CV18 CY7C1314CV18 CY7C1310CV18 CY7C1312CV18 CY7C1910CV18 CY7C1314CV18-250BZXC

    CY7C1310CV18

    Abstract: CY7C1312CV18 CY7C1314CV18 CY7C1910CV18
    Text: CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■


    Original
    PDF CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit CY7C1310CV18 CY7C1312CV18 CY7C1310CV18 CY7C1312CV18 CY7C1314CV18 CY7C1910CV18

    CY7C1312CV18

    Abstract: CY7C1314CV18
    Text: CY7C1312CV18 CY7C1314CV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1312CV18 – 1M x 18 CY7C1314CV18 – 512K x 36 ■ 250 MHz Clock for High Bandwidth


    Original
    PDF CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1312CV18 CY7C1314CV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1312CV18 CY7C1314CV18 18-Mbit QDR II SRAM 2-Word Burst Architecture 18-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1312CV18 – 1M x 18


    Original
    PDF CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1312CV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Configurations Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth


    Original
    PDF CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1310CV18,

    CY7C1312CV18

    Abstract: CY7C1314CV18
    Text: CY7C1312CV18 CY7C1314CV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1312CV18 – 1M x 18 CY7C1314CV18 – 512K x 36 ■ 250 MHz Clock for High Bandwidth


    Original
    PDF CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1312CV18 CY7C1314CV18

    CY7C1310CV18

    Abstract: CY7C1312CV18 CY7C1314CV18 CY7C1910CV18
    Text: CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth


    Original
    PDF CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 18-Mbit 250-MHz RC1910CV18 18/CY7C1910CV18/CY7C1312CV18/CY7C1314CV18 CY7C1310CV18 CY7C1312CV18 CY7C1314CV18 CY7C1910CV18