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Rochester Electronics LLC CY7C130-55PC IC SRAM 8KBIT PARALLEL 48DIP
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DigiKey	CY7C130-55PC	Tube			63	1 - 10 - 100 $4.76 1000 $4.76 10000 $4.76	Buy Now
Infineon Technologies AG CY7C1306CV25-167BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1306CV25-167BZC	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Rochester Electronics LLC CY7C1305BV25-167BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1305BV25-167BZC	Tray			10	1 - 10 $31.96 100 $31.96 1000 $31.96 10000 $31.96	Buy Now
Rochester Electronics LLC CY7C1303TV25-167BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1303TV25-167BZC	Bag			14	1 - 10 - 100 $22.11 1000 $22.11 10000 $22.11	Buy Now
Rochester Electronics LLC CY7C1305TV25-167BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1305TV25-167BZC	Bag			12	1 - 10 - 100 $25.43 1000 $25.43 10000 $25.43	Buy Now

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CY7C130 Datasheets (172)

Part	Manufacturer	Description	Datasheet Type	PDF
CY7C130	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF
CY7C130	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF
CY7C1300A	Cypress Semiconductor	128K x 36 Dual I/O Dual Address Synchronous SRAM	Original	PDF
CY7C1300A-100AC	Cypress Semiconductor	128K x 36 dual I/O dual address synchronous SRAM. Speed 100 MHz.	Original	PDF
CY7C1300A-83AC	Cypress Semiconductor	128K x 36 dual I/O dual address synchronous SRAM. Speed 83 MHz.	Original	PDF
CY7C1301A	Cypress Semiconductor	256K x 36 Dual I/O, Dual Address Synchronous SRAM	Original	PDF
CY7C130-25DC	Cypress Semiconductor	Multiple Array MatriX High-Density EPLDs	Scan	PDF
CY7C130-25LC	Cypress Semiconductor	1024 x 8 Dual-Port Static RAM	Scan	PDF
CY7C130-25LC	Cypress Semiconductor	Multiple Array MatriX High-Density EPLDs	Scan	PDF
CY7C130-25PC	Cypress Semiconductor	Multiple Array MatriX High-Density EPLDs	Scan	PDF
CY7C1302CV25	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF
CY7C1302CV25-100	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF
CY7C1302CV25-133	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF
CY7C1302CV25-133BZC	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF

CY7C1302CV25-167	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF
CY7C1302CV25-167BZC	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF
CY7C1302DV25	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF
CY7C1302DV25-100	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF
CY7C1302DV25-100BZXC	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF
CY7C1302DV25-133	Cypress Semiconductor	9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture	Original	PDF

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CY7C130 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CY7C1304V25 Abstract: No abstract text available Text: 5 CY7C1304V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time	Original	CY7C1304V25 CY7C1304V25	PDF
CY7C1302CV25 Abstract: 1e77 Text: CY7C1302CV25 PREMILINARY 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns clock-to-Valid access time	Original	CY7C1302CV25 167-MHz CY7C1302CV25 1e77	PDF
QDR cypress burst of two Abstract: Cypress QDR CY7C1302V25 CY7C1304V25 Text: QDR SRAMs Fact Sheet Product Overview Cypress's family of Quad Data Rate™ QDR™ SRAMs offers customers the bandwidth improvement that high-speed applications demand. The family currently consists of 2 devices: The CY7C1302V25, with its burst length of 2, and the	Original	CY7C1302V25, CY7C1304V25, 512Kx18 2-200QDRF QDR cypress burst of two Cypress QDR CY7C1302V25 CY7C1304V25	PDF
CY7C1304V25 Abstract: No abstract text available Text: 304V25 CY7C1304V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167 MHz Clock for High Bandwidth — 2.5 ns Clock-to-Valid access time	Original	304V25 CY7C1304V25 CY7C1304V25	PDF
PLCC-52 Abstract: CY7C130 CY7C131 CY7C140 CY7C141 CY7C131-25JC CY7C131-35J Z1014 Text: CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1K x 8 organization ■ 0.65 micron CMOS for optimum speed and power	Original	CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 CY7C130/130A/CY7C131/131A/CY7C140 CY7C130/130A/ CY7C131/131A PLCC-52 CY7C130 CY7C131 CY7C140 CY7C141 CY7C131-25JC CY7C131-35J Z1014	PDF
CY7C1304DV25 Abstract: No abstract text available Text: CY7C1304DV25 PRELIMINARY 9-Mbit Burst of 4 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports The CY7C1304DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists	Original	CY7C1304DV25 CY7C1304DV25	PDF
CY7C1303BV25 Abstract: CY7C1306BV25 Text: CY7C1303BV25 CY7C1306BV25 PRELIMINARY 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	CY7C1303BV25 CY7C1306BV25 18-Mbit 167-MHz CY7C1303BV25/CY7C1306BV25 CY7C1303BV25 CY7C1306BV25	PDF
7C13135 Abstract: CY7C140-35PC 7C130 CY7C130 CY7C131 CY7C140 CY7C141 Text: CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports	Original	CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131/CY7C140 CY7C141 CY7C130/ CY7C131 CY7C140/CY7C141 16-bit 7C13135 CY7C140-35PC 7C130 CY7C130 CY7C140	PDF
CY7C1302V25 Abstract: CY7C1302V25-133BZC Text: yy 7c1302V25: Rev 1.0 Revised: February 15, 2000 CY7C1302V25 Advanced Information 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth	Original	7c1302V25: CY7C1302V25 167-MHz CY7C1302V25 CY7C1302V25-133BZC	PDF
CY7C1305V25-167BZC Abstract: No abstract text available Text: CY7C1305V25 CY7C1307V25 PRELIMINARY 18-Mb Burst of 4 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports • 2.5V core power supply with HSTL Inputs and Outputs The CY7C1305V25/CY7C1307V25 are 2.5V Synchronous	Original	CY7C1305V25 CY7C1307V25 18-Mb 167-MHz BB165D BB165A CY7C1305V25-167BZC	PDF
CY7C Abstract: CY7C130 CY7C131 CY7C140 CY7C141 Text: CY7C130, CY7C130A CY7C131, CY7C131A 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power	Original	CY7C130, CY7C130A CY7C131, CY7C131A CY7C130/130A/CY7C131/131A/CY7C140 CY7C141 CY7C130/130A/CY7C131/131A CY7C CY7C130 CY7C131 CY7C140 CY7C141	PDF
CY7C1304V25 Abstract: No abstract text available Text: CY7C1304V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167 MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time • 4-Word burst for reducing address bus frequency	Original	CY7C1304V25 CY7C1304V25	PDF
CY7C1305AV25 Abstract: CY7C1305AV25-133 CY7C1305AV25-167 CY7C1307AV25 CY7C1307AV25-167 Text: CY7C1305AV25 CY7C1307AV25 PRELIMINARY 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports • 2.5V core power supply with HSTL Inputs and Outputs The CY7C1305AV25/CY7C1307AV25 are 2.5V Synchronous	Original	CY7C1305AV25 CY7C1307AV25 18-Mbit CY7C1305AV25/CY7C1307AV25 BB165D CY7C1305AV25 CY7C1305AV25-133 CY7C1305AV25-167 CY7C1307AV25 CY7C1307AV25-167	PDF
Untitled Abstract: No abstract text available Text: CY7C1302V25 9-Mb Pipelined SRAM with QDR Architecture Features Functional Description • • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	CY7C1302V25 167-MHz CY7C1302V25	PDF

CY7C130 Abstract: CY7C131 CY7C140 CY7C141 Text: CY7C130, CY7C130A CY7C131, CY7C131A 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power	Original	CY7C130, CY7C130A CY7C131, CY7C131A CY7C130/130A/CY7C131/131A CY7C140/CY7C141 CY7C130/130A/CY7C131/131A; 48-pin CY7C13ication CY7C130 CY7C131 CY7C140 CY7C141	PDF
CY7C1302DV25 Abstract: CY7C1302DV25-167 5N25 Text: CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	CY7C1302DV25 167-MHz CY7C1302DV25 CY7C1302DV25-167 5N25	PDF
CY7C1305BV18 Abstract: CY7C1307BV18 Text: CY7C1305BV18 CY7C1307BV18 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	CY7C1305BV18 CY7C1307BV18 18-Mbit 167-MHz CY7C1305BV18 CY7C1307BV18	PDF
cy7c136 Abstract: EME-6300H CY7C13X Text: Qualification Report January 1996 QTP# 95152/95487, Version 1.0 2K/1K x 8 Dual-Port Static RAM MARKETING PART NUMBER DEVICE DESCRIPTION CY7C130/131 1K x 8 Dual-Port Static RAM CY7C140/141 1K x 8 Dual-Port Static RAM CY7C132/142 2K X 8 Dual-Port Static RAM	Original	CY7C130/131 CY7C140/141 CY7C132/142 CY7C136/146 CY7C136 CY7C136-JC CY7C13X CY7C14X cy7c136 EME-6300H	PDF
cy7c131-55nc Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140 Text: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex	OCR Scan	CY7C130/CY7C131 CY7C140/CY7C141 CY7C140/ CY7C141 CY7C130/ CY7C131; IDT7130 IDT7140 cy7c131-55nc ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7140	PDF
ebe switches Abstract: CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35 Text: CYPRESS SEMICONDUCTOR 00 0 3 4 2 1 EbE D 5 • CY7C130/CY7C131 CY7C140/CY7C141 -Z Z A Z . o y n p rrQ C 1024 x 8 Dual-Port Static RAM SEMICONDUCTOR Features Functional Description • 0,8-micron CMOS for optimum speed/power • Automatic power-down • TTL-compatible	OCR Scan	CY7C130/CY7C131 CY7C140/CY7C141 20O1V CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C130/CY7C131/CY7C140/ ebe switches CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35	PDF
Untitled Abstract: No abstract text available Text: CY7C130/CY7C131 CY7C140/CY7C141 CYPRESS SEMICONDUCTOR Features Functional Description • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation	OCR Scan	CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C130/CY 7C131/CY7C140/	PDF
Untitled Abstract: No abstract text available Text: fax id: 5200 CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS 1K x 8 Dual-Port Static Ram Features Functional Description True Dual-Ported memory cells which allow simulta neous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power	OCR Scan	130/C 140/C 65-micron CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin	PDF
7C130 Abstract: L1314 Text: CY7C130/CY7C131 CY7C140/CY7C141 _ 1024 x 8 Dual-Port Static RAM aT ^ p -¿r CYPRESS ^ SEMICONDUCTOR E ach p o rt has independent control pins; chip enable C E , w rite enable (RyW), and output The CY 7C130/CY7C131/CY7C140/ enable (O E ). TVvo flags are p rovided on each	OCR Scan	CY7C130/CY7C131 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C140/CY7C141 7C130/CY7C131/CY7C140/ CY7C14 7C130 L1314	PDF
Untitled Abstract: No abstract text available Text: CY7C130/CY7C131 _ CY7C140/CY7C141 = SEMICONDUCTOR 1024 x 8 D ual-Port Static R A M Features Functional Description • 0.8-micron CMOS for optimum speed/power T he CY 7C 130/CY7C13 L/CY7C140/ CY7C141 arc high-speed C M O S IK by 8 dual-port static RA M s. Two ports are pro	OCR Scan	CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7CI31 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7CI40/CY7C141 130/CY7C13 L/CY7C140/	PDF

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CY7C130 Price and Stock

Rochester Electronics LLC CY7C130-55PC

Infineon Technologies AG CY7C1306CV25-167BZC

Rochester Electronics LLC CY7C1305BV25-167BZC

Rochester Electronics LLC CY7C1303TV25-167BZC

Rochester Electronics LLC CY7C1305TV25-167BZC

CY7C130 Datasheets (172)

CY7C130 Datasheets Context Search

CY7C1304V25

CY7C1302CV25

QDR cypress burst of two

CY7C1304V25

PLCC-52

CY7C1304DV25

CY7C1303BV25

7C13135

CY7C1302V25

CY7C1305V25-167BZC

CY7C

CY7C1304V25

CY7C1305AV25

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CY7C130

CY7C1302DV25

CY7C1305BV18

cy7c136

cy7c131-55nc

ebe switches

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7C130

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