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    CY7C1270KV18 Price and Stock

    Rochester Electronics LLC CY7C1270KV18-400BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1270KV18-400BZC Tray 6
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    Infineon Technologies AG CY7C1270KV18-400BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    Infineon Technologies AG CY7C1270KV18-550BZC

    IC SRAM 36MBIT PAR 165FBGA
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    Rochester Electronics LLC CY7C1270KV18-550BZC

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1270KV18-550BZC Tray 4
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    Infineon Technologies AG CY7C1270KV18-400BZXI

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1270KV18-400BZXI Tray 680
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    Avnet Americas CY7C1270KV18-400BZXI Tray 680
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    CY7C1270KV18 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1270KV18-400BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 400MHZ 165FBGA Original PDF
    CY7C1270KV18-400BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 400MHZ 165FBGA Original PDF
    CY7C1270KV18-400BZXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 400MHZ 165FBGA Original PDF
    CY7C1270KV18-550BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 550MHZ 165FBGA Original PDF

    CY7C1270KV18 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)


    Original     		CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1266KV18 CY7C1277KV18 CY7C1268KV18 3M Touch Systems PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1268KV18/CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 Cycles:


    Original     		CY7C1268KV18/CY7C1270KV18 36-Mbit CY7C1268KV18 CY7C1270KV18 PDF

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 Cycles:


    Original     		CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1268KV18 3M Touch Systems PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)


    Original     		CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1266KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 Cycles:


    Original     		CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1268KV18 PDF

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36 Mbit density (4 M x 8, 4 M × 9, 2 M × 18, 1 M × 36)


    Original     		CY7C1266KV18, CY7C1277KV18 CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1266KV18 CY7C1277KV18 CY7C1268KV18 3M Touch Systems PDF

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1268KV18, CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36) With Read Cycle Latency of 2.5 Cycles:


    Original     		CY7C1268KV18, CY7C1270KV18 36-Mbit CY7C1268KV18 3M Touch Systems PDF