CY7C1248V18 Search Results

CY7C1248V18 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1248V18		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)		Original	PDF

CY7C1248V18 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: THIS SPEC IS OBSOLETE Spec No: 001-06348 Spec Title: CY7C1248V18, CY7C1250V18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Sunset Owner: Jayasree Nayar Replaced by: None CY7C1248V18 CY7C1250V18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)	Original	PDF	CY7C1248V18, CY7C1250V18 36-Mbit CY7C1248V18 CY7C1250V18
CY7C1250V18-333BZC Abstract: CY7C1246V18 CY7C1248V18 CY7C1250V18 CY7C1257V18 Text: CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 375 MHz clock for high bandwidth	Original	PDF	CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 36-Mbit CY7C1246V18, CY7C1257V18, CY7C1248V18, CY7C1250V18 CY7C1250V18-333BZC CY7C1246V18 CY7C1248V18 CY7C1257V18
CY7C1250V18-333BZC Abstract: CY7C1248V18 CY7C1250V18 Text: CY7C1248V18 CY7C1250V18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 36-Mbit Density (2M x 18, 1M x 36) ■ 300 MHz to 375 MHz Clock for high Bandwidth ■ 2-word Burst for reducing Address Bus Frequency	Original	PDF	CY7C1248V18 CY7C1250V18 36-Mbit CY7C1248V18, CY7C1250V18 CY7C1250V18-333BZC CY7C1248V18
Untitled Abstract: No abstract text available Text: CY7C1257V18 CY7C1248V18 CY7C1250V18 PRELIMINARY 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 36-Mbit density (4M x 9, 2M x 18, 1M x 36) The CY7C1257V18, CY7C1248V18, and CY7C1250V18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II+	Original	PDF	CY7C1257V18 CY7C1248V18 CY7C1250V18 36-Mbit CY7C1257V18/CY7C1248V18/CY7C1250V18
CY7C1246V18 Abstract: CY7C1248V18 CY7C1250V18 CY7C1257V18 Text: CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) ■ 300 MHz to 375 MHz clock for high bandwidth	Original	PDF	CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 36-Mbit CY7C1257V18, CY7C1250V18 CY7C1246V18 CY7C1248V18 CY7C1257V18
CY7C1248V18 Abstract: CY7C1250V18 Cypress QDR Text: CY7C1248V18 CY7C1250V18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 36-Mbit Density (2M x 18, 1M x 36) ■ 300 MHz to 375 MHz Clock for high Bandwidth ■ 2-word Burst for reducing Address Bus Frequency	Original	PDF	CY7C1248V18 CY7C1250V18 36-Mbit CY7C1248V18, CY7C1250V18 CY7C1248V18 Cypress QDR
renesas ordering guide Abstract: CY7C1248V18-BWS0 Text: CY7C1248V18 CY7C1250V18 PRELIMINARY 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (2M x 18, 1M x 36) 300 MHz to 375 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1248V18 CY7C1250V18 36-Mbit 165-bas renesas ordering guide CY7C1248V18-BWS0
Untitled Abstract: No abstract text available Text: CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 375 MHz clock for high bandwidth	Original	PDF	CY7C1246V18 CY7C1257V18 CY7C1248V18 CY7C1250V18 36-Mbit