Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    CL018G Search Results

    CL018G Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CL018G

    Abstract: TSMC 0.18 um CMOS silicon TSMC 0.18 um CMOS low power low noise frequency divider specification cmos tsmc 0.18 tsmc cmos model N-7075 0.18 um CMOS Process adc verilog tsmc cmos 0.18 um
    Text: BRIEF PRODUCT SPECIFICATION nPLL20240-18a 240MHz Low Jitter PLL FEATURES • • • • • • • • • TSMC CL018G 1.8 V 240 MHz Low Jitter PLL Reference Clock Input 20 Mhz, 40 MHz and 80 MHz Programmable Steps, 3, 6 or 12 Divider 80 MHz, 40 MHz and 20 MHz Complimentary


    Original     		PDF nPLL20240-18a 240MHz CL018G N-7075 TSMC 0.18 um CMOS silicon TSMC 0.18 um CMOS low power low noise frequency divider specification cmos tsmc 0.18 tsmc cmos model 0.18 um CMOS Process adc verilog tsmc cmos 0.18 um

    CL018G

    Abstract: nrzi encoding GT3200 GT3200-DIE GT3200-JD nrzi encoding in usb
    Text: GT3200-DIE USB 2.0 PHY IC Die Data Brief Product Features Designed on the TSMC 0.18µ Generic Logic Process CL018G with 1.8V core and 3.3V I/O NRZI encoding and decoding USB-IF “Hi-Speed” certified to USB 2.0 electrical specification Supports the USB suspend state, HS detection,


    Original     		PDF GT3200-DIE CL018G) 60MHz 30MHz 16-bit 480Mbps 12Mbps 185mW) GT3200-DIE GT3200 CL018G nrzi encoding GT3200-JD nrzi encoding in usb

    MoSys

    Abstract: CL018G tsmc 0.18um MoSys sram embedded BWEB M1T1HT18PZ32E C-l018 32K32 MoSys 1T sram
    Text: High Speed Pipelined 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PZ32E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late-late write mode timing • 32-Bit wide data buses


    Original     		PDF 32Kx32) M1T1HT18PZ32E 32-Bit CL018G 2300um 32Kx32 1650um M1T1HT18PZ32E MoSys tsmc 0.18um MoSys sram embedded BWEB C-l018 32K32 MoSys 1T sram

    mosys sram embedded

    Abstract: CL018G M1T2HT18FE64E
    Text: High Speed Flow-through 2-Mbit 32Kx64 Standard 1T-SRAM Embedded Memory Macro M1T2HT18FE64E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 64-Bit wide data buses


    Original     		PDF 32Kx64) M1T2HT18FE64E 64-Bit CL018G 3200um 2300um 32Kx64 M1T2HT18FE64E mosys sram embedded

    MoSys 1T sram

    Abstract: 64Kx32 CL018G M1T2HT18FE32E C-l018 "1t-sram"
    Text: High Speed Flow-through 2-Mbit 64Kx32 Standard 1T-SRAM Embedded Memory Macro M1T2HT18FE32E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 32-Bit wide data buses


    Original     		PDF 64Kx32) M1T2HT18FE32E 32-Bit CL018G M1T2HT18FE32E 3200um MoSys 1T sram 64Kx32 C-l018 "1t-sram"

    16Kx32

    Abstract: TSMC 0.18um CL018G M1T1HT18FE64E
    Text: High Speed Flow-through 1-Mbit 16Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18FE64E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 64-Bit wide data buses


    Original     		PDF 16Kx32) M1T1HT18FE64E 64-Bit CL018G M1T1HT18FE64E 16Kx32 TSMC 0.18um

    "1t-sram"

    Abstract: TSMC 0.18um CL018G M1T2HT18FL64E MoSys
    Text: High Speed Flow-through 2-Mbit 32Kx64 Standard 1T-SRAM Embedded Memory Macro M1T2HT18FL64E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 64-Bit wide data buses


    Original     		PDF 32Kx64) M1T2HT18FL64E 64-Bit CL018G M1T2HT18FL64E 2300um 32Kx64 3200um "1t-sram" TSMC 0.18um MoSys

    CL018G

    Abstract: M1T1HT18FL32E MoSys sram embedded TSMC 0.18um Process parameters
    Text: High Speed Flow-through 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18FL32E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 32-Bit wide data buses


    Original     		PDF 32Kx32) M1T1HT18FL32E 32-Bit CL018G M1T1HT18FL32E MoSys sram embedded TSMC 0.18um Process parameters

    CL018G

    Abstract: M1T1LT18FL32E
    Text: Low Power Flow-through 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1LT18FL32E • Low Power 1T-SRAM Standard Macro • 10-83 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 32-Bit wide data buses


    Original     		PDF 32Kx32) M1T1LT18FL32E 32-Bit CL018G M1T1LT18FL32E

    tsmc 0.18um

    Abstract: CL018G M1T1HT18FE32E
    Text: High Speed Flow-through 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18FE32E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 32-Bit wide data buses


    Original     		PDF 32Kx32) M1T1HT18FE32E 32-Bit CL018G M1T1HT18FE32E tsmc 0.18um

    TSMC cmos 0.18um

    Abstract: TSMC 0.18um SRAM TSMC 180nm single port sram TSMC 180nm dual port sram TSMC 0.18Um tsmc 180nm sram 2 port register file SC18 180-nm TSMC 180nm
    Text: AMI Semiconductor SC18 0.18µm CMOS Standard Cell SC18 0.18µm CMOS Standard Cell Feature Sheet Key Features • Excellent performance: • 5.6ns delay for an 18 x 18 multiplier • Junction temperature range -40°C to 125°C • AMIS 180nm ASICs provide the optimal combination of


    Original     		PDF 180nm 200-300MHz 30nW/MHz/gate CL018G PCI33, PCI66, PCIX-183 M-20620-001 TSMC cmos 0.18um TSMC 0.18um SRAM TSMC 180nm single port sram TSMC 180nm dual port sram TSMC 0.18Um tsmc 180nm sram 2 port register file SC18 180-nm TSMC 180nm

    CL018G

    Abstract: M1T1HT18PL64E 16Kx64 M1T1HT18PL32E fast sram 100mhz mosys sram embedded
    Text: High Speed Pipelined 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PL64E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late write mode timing • 64-Bit wide data buses


    Original     		PDF 16Kx64) M1T1HT18PL64E 64-Bit CL018G M1T1HT18PL64E 16Kx64 2200um 16Kx64 M1T1HT18PL32E fast sram 100mhz mosys sram embedded

    CL018G

    Abstract: M1T2LT18FE64E MoSys 1T sram
    Text: Low Power Flow-through 2-Mbit 32Kx64 Standard 1T-SRAM Embedded Memory Macro M1T2LT18FE64E • Low Power 1T-SRAM Standard Macro • 10-83 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 64-Bit wide data buses


    Original     		PDF 32Kx64) M1T2LT18FE64E 64-Bit CL018G M1T2LT18FE64E 3330um MoSys 1T sram

    CL018G

    Abstract: M1T1HT18PE64E Signal Technology 16Kx64
    Text: High Speed Pipelined 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PE64E • High Speed 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Early write mode timing • 64-Bit wide data buses


    Original     		PDF 16Kx64) M1T1HT18PE64E 64-Bit CL018G M1T1HT18PE64E Signal Technology 16Kx64

    CL018G

    Abstract: 64Kx32 M1T2HT18PE32E TSMC 0.18um 1T-sram tsmc sram "1t-sram"
    Text: High Speed Pipelined 2-Mbit 64Kx32 Standard 1T-SRAM Embedded Memory Macro M1T2HT18PE32E • High Speed 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Early write mode timing • 32-Bit wide data buses


    Original     		PDF 64Kx32) M1T2HT18PE32E 32-Bit CL018G M1T2HT18PE32E 3200um 2300um 64Kx32 64Kx32 TSMC 0.18um 1T-sram tsmc sram "1t-sram"

    CL018G

    Abstract: M1T2HT18PL64E mosys sram embedded sram embedded
    Text: High Speed Pipelined 2-Mbit 32Kx64 Standard 1T-SRAM Embedded Memory Macro M1T2HT18PL64E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late write mode timing • 64-Bit wide data buses


    Original     		PDF 32Kx64) M1T2HT18PL64E 64-Bit CL018G M1T2HT18PL64E 3200um 2300um 32Kx64 mosys sram embedded sram embedded

    CL018G

    Abstract: M1T1HT18PE32E Signal Technology fast sram 100mhz
    Text: High Speed Pipelined 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PE32E • High Speed 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Early write mode timing • 32-Bit wide data buses


    Original     		PDF 32Kx32) M1T1HT18PE32E 32-Bit CL018G M1T1HT18PE32E Signal Technology fast sram 100mhz

    CL018G

    Abstract: M1T1LT18FE32E
    Text: Low Power Flow-through 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1LT18FE32E • Low Power 1T-SRAM Standard Macro • 10-83 MHz operation • 1-Clock cycle time • Flow-through read access timing • Early write mode timing • 32-Bit wide data buses


    Original     		PDF 32Kx32) M1T1LT18FE32E 32-Bit CL018G M1T1LT18FE32E

    CL018G

    Abstract: M1T2LT18FL32E M1T2LT18FL64E mosys sram embedded tsmc 0.18um
    Text: Low Power Flow-through 2-Mbit 32Kx64 Standard 1T-SRAM Embedded Memory Macro M1T2LT18FL64E • Low Power 1T-SRAM Standard Macro • 10-83 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 64-Bit wide data buses


    Original     		PDF 32Kx64) M1T2LT18FL64E 64-Bit CL018G M1T2LT18FL64E 3330um M1T2LT18FL32E mosys sram embedded tsmc 0.18um

    CL018G

    Abstract: M1T1HT18FL64E MoSys MoSys sram embedded
    Text: High Speed Flow-through 1-Mbit 16Kx64 Standard 1T-SRAM Embedded Memory Macro M1T1HT18FL64E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 64-Bit wide data buses


    Original     		PDF 16Kx64) M1T1HT18FL64E 64-Bit CL018G M1T1HT18FL64E MoSys MoSys sram embedded

    CL018G

    Abstract: M1T2HT18FL32E "1t-sram"
    Text: High Speed Flow-through 2-Mbit 64Kx32 Standard 1T-SRAM Embedded Memory Macro M1T2HT18FL32E • High Speed 1T-SRAM Standard Macro • 100 MHz operation • 1-Clock cycle time • Flow-through read access timing • Late write mode timing • 32-Bit wide data buses


    Original     		PDF 64Kx32) M1T2HT18FL32E 32-Bit CL018G M1T2HT18FL32E 2300um 32Kx64 "1t-sram"

    CL018G

    Abstract: M1T2HT18PE64E TSMC 0.18um tsmc sram CL018 TSMC 0.18um Process parameters
    Text: High Speed Pipelined 2-Mbit 32Kx64 Standard 1T-SRAM Embedded Memory Macro M1T2HT18PE64E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Early write mode timing • 64-Bit wide data buses


    Original     		PDF 32Kx64) M1T2HT18PE64E 64-Bit CL018G M1T2HT18PE64E 3200um TSMC 0.18um tsmc sram CL018 TSMC 0.18um Process parameters

    C-l018

    Abstract: fast sram 100mhz CL018G M1T1HT18PL32E mosys sram embedded
    Text: High Speed Pipelined 1-Mbit 32Kx32 Standard 1T-SRAM Embedded Memory Macro M1T1HT18PL32E • High Performance 1T-SRAM Standard Macro • 200 MHz operation • 1-Clock cycle time • Pipelined read access timing • Late write mode timing • 32-Bit wide data buses


    Original     		PDF 32Kx32) M1T1HT18PL32E 32-Bit CL018G M1T1HT18PL32E 32Kx32 2200um C-l018 fast sram 100mhz mosys sram embedded

    C-l018

    Abstract: CL018G DS28CN01 DS28E01-100 M1470 DS1961S DS1963S DS2460 DS28E02 DS28E10
    Text: 19-5870; Rev 0; 5/11 Memory-Mapped SHA-1 Coprocessor The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level RTL implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA-1 computation required for authenticating


    Original     		PDF 64-byte DS1963S, DS1961S, DS28E10, DS28E02, DS2460, DS28CN01, DS28E01-100. 20-byte C-l018 CL018G DS28CN01 DS28E01-100 M1470 DS1961S DS1963S DS2460 DS28E02 DS28E10