AD9289
Abstract: AD9289BBC-65 AD9289BBC-65EB ANSI644 ANSI-644
Text: Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter AD9289 Preliminary Technical Data FEATURES FUNCTIONAL BLOCK DIAGRAM • Four ADCs in one package DRGND AVDD • Serial LVDS digital output data rates up to 520 Mbps ANSI644 PDWN DRVDD OR+ OR- S1 AD9289 • Data clock output provided
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AD9289
ANSI644)
AD9289BBC-65
AD9289BBC-65EB
PR03682-0-6/04
AD9289
AD9289BBC-65
AD9289BBC-65EB
ANSI644
ANSI-644
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cwi 1011
Abstract: 128 pin ultrasound probe AN-835 ANSI-644 JESD51-2 AD9278-50EBZ LAG 665 equivalent ultrasound receiver vga motion DOPPLER radar system block diagram X band active phased a
Text: Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator AD9278 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator Low power: 88 mW per channel, TGC mode, 40 MSPS; 32 mW per channel, CW mode 10 mm x 10 mm, 144-ball CSP-BGA TGC channel input-referred noise: 1.3 nV/√Hz, max gain
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AD9278
144-ball
dB/17
dB/21
p-p/450
21LANARITY
MO-275-EEAB-1
10-21-2010-B
BC-144-1)
cwi 1011
128 pin ultrasound probe
AN-835
ANSI-644
JESD51-2
AD9278-50EBZ
LAG 665 equivalent
ultrasound receiver vga
motion DOPPLER
radar system block diagram X band active phased a
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max9291
Abstract: AD6643-200 CP-64-4 901MH AN83-5 10-com 1401M 10True
Text: Dual IF Receiver AD6643 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD6643 VIN+A VIN–A PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 VCM VIN+B VIN–B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DATA MULTIPLEXER AND LVDS DRIVERS DCO± D0±
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11-bit,
ANSI-644
64-Lead
AD6643-200
AD6643-250
CP-64-4
max9291
901MH
AN83-5
10-com
1401M
10True
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17D06
Abstract: 16D06 D01N
Text: FEATURES APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Handheld scope meters
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14-Bit,
MSPS/125
AD9645
14-BIT
ANSI-644,
CP-32-12)
AD9645BCPZ-80
AD9645BCPZRL7-80
AD9645BCPZ-125
17D06
16D06
D01N
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0x105
Abstract: 500MSPS AN-835 ANSI-644 PD10 CP-56-1 4501M
Text: 250 MHz Bandwidth DPD Observation Receiver AD6641 FEATURES GENERAL DESCRIPTION SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS −1.0 dBFS SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS) Excellent linearity
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AD6641
12-bit
56-Lead
CP-56-1)
AD6641BCPZ-500
AD6641BCPZRL7-500
AD6641-500EBZ
D09813-0-4/11
0x105
500MSPS
AN-835
ANSI-644
PD10
CP-56-1
4501M
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max8895
Abstract: AD9613BCPZ-250
Text: FEATURES SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS SFDR = 86 dBc at 185 MHz fIN and 250 MSPS −149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 770 mW at 250 MSPS 1.8 V supply voltages LVDS ANSI-644 levels outputs
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12-Bit,
MSPS/210
MSPS/250
AD9613
12-BIT
ANSI-644
64-Lead
max8895
AD9613BCPZ-250
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AD9467
Abstract: B0205F5050A00 AD520* differential amplifier
Text: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter AD9467 Data Sheet 75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS SFDR at 170 MHz at 250 MSPS 92 dBFS at −1 dBFS 100 dBFS at −2 dBFS 60 fs rms jitter Excellent linearity at 250 MSPS
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ANSI-644
16-Bit,
MSPS/250
AD9467
CP-72-5)
AD9467BCPZ-200
AD9467BCPZRL7-200
AD9467BCPZ-250
AD9467BCPZRL7-250
AD9467-200EBZ
AD9467
B0205F5050A00
AD520* differential amplifier
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circuit diagram of analog clock using logic gates
Abstract: No abstract text available
Text: FEATURES SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS SFDR = 85 dBc at 185 MHz AIN and 250 MSPS −151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 785 mW at 250 MSPS 1.8 V supply voltages LVDS ANSI-644 levels outputs
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14-Bit,
MSPS/210
MSPS/250
AD9643
14-BIT
ANSI-644
64-Lead
circuit diagram of analog clock using logic gates
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smd diode c644
Abstract: diode c649 smd diode c548 C748 SMC transistor C734 smd diode c549 C706 diode c624 DIODE smd diode C645 diode c741
Text: Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter AD9222 8 ADCs integrated into 1 package 93 mW ADC power per channel at 50 MSPS SNR = 70 dB to Nyquist ENOB = 11.3 bits SFDR = 84 dBc Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical)
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12-Bit,
AD9222
ANSI-644,
AD9222BCPZ-40
AD9222BCPZRL7-401
AD9222BCPZ-501
AD9222BCPZRL7-501
AD9222-50EBZ
64-Lead
smd diode c644
diode c649
smd diode c548
C748 SMC
transistor C734
smd diode c549
C706 diode
c624 DIODE
smd diode C645
diode c741
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center tap transformer 18 0 18
Abstract: C532 diode 6562D 9018D
Text: Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V A/D Converter AD9259 4 ADCs integrated into 1 package 98 mW ADC power per channel at 50 MSPS SNR = 73 dB to Nyquist ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = ±0.5 LSB (typical) INL = ±1.5 LSB (typical)
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14-Bit,
AD9259
ANSI-644,
48-Lead
CP-48-1)
AD9259BCPZ-50
AD9259BCPZRL7-501
AD9259-50EBZ1
center tap transformer 18 0 18
C532 diode
6562D
9018D
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AD951x
Abstract: No abstract text available
Text: Quad IF Receiver AD6657A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND AD6657A VIN+A PIPELINE ADC VIN–A 14 NOISE SHAPING REQUANTIZER DO±AB VCMA VIN+B PIPELINE ADC VIN–B 14 NOISE SHAPING REQUANTIZER 11 VCMB VIN+C PIPELINE ADC VIN–C
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11-bit,
ANSI-644
10-21-2010-B
MO-275-EEAB-1
144-Ball
BC-144-1)
AD6657ABBCZ
AD6657ABBCZRL
AD6657AEBZ
AD951x
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B616A
Abstract: temperature controller CHB 402 manual PVA2A tl701 p406 diode potentiometer SMC 10 V ADP3335-3 VR451 J501 1r313
Text: Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9271 PDWN STBY AD9271 LOSW-C LO-C LI-C LG-C LOSW-D LO-D LI-D LG-D LNA VGA AAF LNA VGA AAF LNA VGA AAF LOSW-E LO-E LI-E LG-E LOSW-F LO-F LI-F LG-F LOSW-G LO-G LI-G LG-G LNA VGA AAF LNA VGA AAF LNA VGA AAF LOSW-H
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AD9271
dB/15
dB/18
p-p/250
ANSI-644,
100-Lead
B616A
temperature controller CHB 402 manual
PVA2A
tl701
p406 diode
potentiometer SMC 10 V
ADP3335-3
VR451
J501
1r313
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c606 Schottky diode
Abstract: avago bar code on the box smd diode c644
Text: Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC AD9252 8 analog-to-digital converters ADCs integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical)
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14-Bit,
AD9252
ANSI-644,
MO-220-VMMD-4
64-Lead
CP-64-3)
AD9252BCPZ-50
AD9252BCPZRL7-501
AD9252-50EBZ1
c606 Schottky diode
avago bar code on the box
smd diode c644
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YAGEO CHIP RESISTORS instruction
Abstract: AD9287
Text: Preliminary Technical Data Quad 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter AD9228 FEATURES FUNCTIONAL BLOCK DIAGRAM Four ADCs in one package Serial LVDS ANSI-644 ,IEEE 1596.3 reduced range link Data and frame clock outputs SNR = 70 dB (to Nyquist)
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ANSI-644
12-bit,
AD9228
MO-220-VKKD-2
48-Lead
CP-48-1)
AD9228BCPZ-40
AD9228BCPZ-65
AD9228-65EB
CP-48
YAGEO CHIP RESISTORS instruction
AD9287
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AN-877
Abstract: ad9524
Text: IF Diversity Receiver AD6649 FEATURES APPLICATIONS SNR = 73.0 dBFS in a 95 MHz bandwidth at 185 MHz AIN and 245.76 MSPS SFDR = 85 dBc at 185 MHz AIN and 250 MSPS Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 1 W with fixed-frequency NCO,
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AD6649
ANSI-644
32-bit
MO-220-VMMD-4
64-Lead
CP-64-4)
AD6649BCPZ
AD6649BCPZRL7
AD6649EBZ
AN-877
ad9524
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AN-877 ANALOG DEVICES
Abstract: No abstract text available
Text: Dual IF Receiver AD6643 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD6643 VIN+A VIN–A PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 VCM VIN+B VIN–B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DATA MULTIPLEXER AND LVDS DRIVERS DCO± D0± D10± OEB
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AD6643
ANSI-644
MO-220-VMMD-4
64-Lead
CP-64-4)
AD6643BCPZ-200
AD6643BCPZRL7-200
AD6643-200EBZ
AN-877 ANALOG DEVICES
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40 nsr 120 rd
Abstract: AD951x
Text: Dual IF Receiver AD6642 FEATURES APPLICATIONS Communications Diversity radio and smart antenna MIMO systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios FUNCTIONAL BLOCK DIAGRAM
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AD6642
11-bit,
ANSI-644
MO-205-AC.
144-Ball
BC-144-1)
AD6642BBCZ
AD6642BBCZRL
AD6642EBZ
40 nsr 120 rd
AD951x
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AD9480
Abstract: E1-E16 AD8138 AD8351 AD9480ASUZ-250 AD9480BSUZ-250 ANSI-644 LVEL16 MC100LVEL16 R45X
Text: 8-Bit, 250 MSPS 3.3 V A/D Converter AD9480 FUNCTIONAL BLOCK DIAGRAM DNL = ± 0.25 LSB INL = ± 0.26 LSB Single 3.3 V supply operation 3.0 V to 3.6 V Power dissipation of 590 mW at 250 MSPS 1 V p-p analog input range Internal 1.0 V reference Single-ended or differential analog inputs
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AD9480
SU-44)
AD9480BSUZ-2501,
AD9480ASUZ-2501
AD9480-LVDS/PCB3
44-Lead
AD9480BSUZ-250
SU-44
AD9480
E1-E16
AD8138
AD8351
AD9480ASUZ-250
ANSI-644
LVEL16
MC100LVEL16
R45X
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AD9230-250EBZ
Abstract: AD9211 AD9230 AD9230-170 AD9230-210 AD9230-250 AN-835 ANSI-644 0125P
Text: 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter AD9230 FEATURES FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AVDD 1.8V AD9230 REFERENCE CML VIN+ VIN– DRVDD DRGND TRACK-AND-HOLD ADC 12-BIT CORE CLK+ CLK– 12 OUTPUT 12 STAGING LVDS CLOCK
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12-Bit,
MSPS/210
MSPS/250
AD9230
12-BIT
ANSI-644
170EBZ1
AD9230-210EBZ1
AD9230-250EBZ1
AD9230-250EBZ
AD9211
AD9230
AD9230-170
AD9230-210
AD9230-250
AN-835
0125P
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AD9273
Abstract: AD927 ultrasound transducer transformer AN-835 ANSI-644 cw doppler xamp 600MBPS FR-415 96 pin ultrasound probe
Text: Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9273 LOSW-C LO-C LI-C LG-C LOSW-D LO-D LI-D LG-D LOSW-E LO-E LI-E LG-E LOSW-F LO-F LI-F LG-F LOSW-G LO-G LI-G LG-G LNA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LOSW-H LO-H LI-H
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AD9273
12-BIT
144-Ball
AD9273
AD927
ultrasound transducer transformer
AN-835
ANSI-644
cw doppler
xamp
600MBPS
FR-415
96 pin ultrasound probe
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AD9289
Abstract: AD9289BBC ANSI-644 pipeline adc
Text: Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter Preliminary Technical Data FEATURES • • • • • • • • • • Four ADCs in one package Serial LVDS digital output data rates up to 520 MHz ANSI-644 Data clock output provided SNR = 47 dB (to Nyquist)
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ANSI-644)
AD9289
AD9289
AD9289BBC
AD9289/PCB
C02959-0-11/02
AD9289BBC
ANSI-644
pipeline adc
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Untitled
Abstract: No abstract text available
Text: 16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter ADC AD9652 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD3 AVDD SDIO SCLK CSB DRVDD SPI AD9652 OR+, OR– PROGRAMMING DATA VIN+A DDR DATA INTERLEAVER LVDS OUTPUT DRIVER ADC VIN–A VREF SENSE
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16-Bit,
AD9652
1-18-2011-A
144-Ball
BC-144-6)
AD9652BBCZ-310
AD9652BBCZRL7-310
AD9652-310EBZ
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Untitled
Abstract: No abstract text available
Text: Dual, 14-Bit, 80 MSPS/125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter AD9645 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
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14-Bit,
MSPS/125
AD9645
CDMA2000,
14-BIT
AD9645BCPZ-80
AD9645BCPZRL7-80
AD9645BCPZ-125
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Untitled
Abstract: No abstract text available
Text: FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 71.0 dBFS at 185 MHz AIN and 250 MSPS SFDR = 83 dBc at 185 MHz AIN and 250 MSPS −152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS AIN, 250 MSPS Total power consumption: 390 mW at 250 MSPS 1.8 V supply voltages LVDS ANSI-644 levels outputs
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ANSI-644
14-BIT
32-Lead
AD9642
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