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    AN1503 Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    AN1503 Motorola AN1503 ECLinPS I-O SPICE Modeling Kit Original PDF
    AN-1503 National Semiconductor Application Note 1503 Designing an AdvancedTCA Compliant M-LVDS Clock Distribution Network Original PDF
    AN1503 On Semiconductor ECLinPS I-O SPICE Modelling Kit Original PDF

    AN1503 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    K1117

    Abstract: k2225 transistor K2225 k1317 K0217 TRANSISTOR K0312 K1618 K0311 transistor k1117 transistor k0319
    Text: AN1503/D ECLinPS and ECLinPS Lite SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information


    Original     		PDF AN1503/D r14525 AN1503/D K1117 k2225 transistor K2225 k1317 K0217 TRANSISTOR K0312 K1618 K0311 transistor k1117 transistor k0319

    transistor k1317

    Abstract: K2225 k1317 transistors k2628 k1117 transistors K1317 k1118 k2225 transistor k1117 transistor transistor k1117
    Text: AN1503/D ECLinPS and ECLinPS Lite SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information


    Original     		PDF AN1503/D r14525 transistor k1317 K2225 k1317 transistors k2628 k1117 transistors K1317 k1118 k2225 transistor k1117 transistor transistor k1117

    k1117

    Abstract: k2225 k2225 transistor k1117 transistor k1317 transistor k1317 transistor k1117 k1118 transistor k1213 k1213
    Text: AN1503/D ECLinPS and ECLinPS Lite] SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information


    Original     		PDF AN1503/D r14525 k1117 k2225 k2225 transistor k1117 transistor k1317 transistor k1317 transistor k1117 k1118 transistor k1213 k1213

    Transistor E112

    Abstract: TN13P5 E212 transistor E416 AN1503 spice e154 E155 Modelling DL140
    Text: AN1503 Application Note  ECLinPS I/O SPICE Modelling Kit Prepared by Todd Pearson ECLinPS Applications Engineering This application note provides the SPICE information necessary to accurately model system interconnect situations for high speed ECLinPS designs. The note


    Original     		PDF AN1503 DL140 AN1503/D* AN1503/D Transistor E112 TN13P5 E212 transistor E416 AN1503 spice e154 E155 Modelling

    transistors k2628

    Abstract: k1118 k1317 k0317 k2225 transistor transistor k1317 k1117 k2225 transistor K2628 k2324
    Text: AN1503/D ECLinPS and ECLinPS Lite SPICE Modeling Kit Prepared by Senad Lomigora, Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE Objective The objective of this kit is to provide customers with enough circuit schematic and SPICE parameter information


    Original     		PDF AN1503/D r14525 transistors k2628 k1118 k1317 k0317 k2225 transistor transistor k1317 k1117 k2225 transistor K2628 k2324

    100EL91

    Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
    Text: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them


    Original     		PDF MC100EL91 MC100EL91 MC100LVEL91. r14525 MC100EL91/D 100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91

    E212 transistor

    Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
    Text: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


    Original     		PDF MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 r14525 MC10E112/D E212 transistor E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400

    AND8020

    Abstract: EL90 MC100EL90 MC100EL90DW MC100EL90DWR2 100EL90
    Text: MC100EL90 -3.3V / -5VĄTriple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either –3.3 V or –5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL


    Original     		PDF MC100EL90 MC100EL90 r14525 MC100EL90/D AND8020 EL90 MC100EL90DW MC100EL90DWR2 100EL90

    KPT25

    Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
    Text: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal


    Original     		PDF MC100EPT25 MC100EPT25 EPT25 r14525 MC100EPT25/D KPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw

    marking CODE D2B

    Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
    Text: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be


    Original     		PDF MC10E104, MC100E104 MC10E/100E104 MC10E104FN EIA/JESD78 r14525 MC10E104/D marking CODE D2B MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND

    KVT23

    Abstract: MC100LVELT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT
    Text: MC100LVELT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which


    Original     		PDF MC100LVELT23 MC100LVELT23 LVELT23 MC100LVELT23/D KVT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT

    MC100E116

    Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
    Text: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.


    Original     		PDF MC10E116, MC100E116 MC10E/100E116 r14525 MC10E116/D MC100E116 MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116

    MC100LVEL01

    Abstract: MC100LVEL01D 1085 SPICE model
    Text: MC100LVEL01 3.3VĄECL 4-Input OR/NOR The MC100LVEL01 is a 4–input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in


    Original     		PDF MC100LVEL01 MC100LVEL01 LVEL01 KVL01 r14525 MC100LVEL01/D MC100LVEL01D 1085 SPICE model

    KEL04

    Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
    Text: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those


    Original     		PDF MC10EL04, MC100EL04 MC10EL/100EL04 AND8003/D r14525 MC10EL04/D KEL04 HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04

    100EL91

    Abstract: MC100EL91 MC100LVEL91
    Text: MC100EL91 5 V Triple PECL Input to −5 V ECL Output Translator Description The MC100EL91 is a triple PECL input to ECL output translator. The device receives standard voltage differential PECL signals, determined by the VCC supply level, and translates them to differential


    Original     		PDF MC100EL91 MC100EL91 MC100LVEL91. MC100EL91/D 100EL91 MC100LVEL91

    MC10EP016

    Abstract: MC100EP016 MC10E016
    Text: MC10EP016, MC100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD


    Original     		PDF MC10EP016, MC100EP016 MC10/100EP016 MC10E016 MC10EP016/D MC10EP016 MC100EP016

    KVL11

    Abstract: KV11 LVEL11 MC100LVEL11
    Text: MC100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer Description The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times


    Original     		PDF MC100LVEL11 MC100LVEL11 LVEL11 KVL11 MC100LVEL11/D KVL11 KV11

    EP29

    Abstract: MC100EP29 MC10EP29
    Text: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.


    Original     		PDF MC10EP29, MC100EP29 MC10/100EP29 MC10/100EL29. MC10EP29/D EP29 MC100EP29 MC10EP29

    KV05

    Abstract: KVL05 MC100EL05 MC100LVEL05 MC100LVEL05MNR4G
    Text: MC100LVEL05 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally


    Original     		PDF MC100LVEL05 MC100LVEL05 MC100EL05 LVEL05 MC100LVEL05/D KV05 KVL05 MC100LVEL05MNR4G

    MC100E416

    Abstract: MC10E416 MC10E416FN
    Text: MC10E416, MC100E416 5V ECL Quint Differential Line Receiver Description The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.


    Original     		PDF MC10E416, MC100E416 MC10E416/100E416 MC10E416/D MC100E416 MC10E416 MC10E416FN

    405C

    Abstract: 485G NB6L239
    Text: NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8


    Original     		PDF NB6L239 NB6L239 B2/4/8/16. NB6L239/D 405C 485G

    LVEP210

    Abstract: MC100 MC100EP210 MC100LVEP210
    Text: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is


    Original     		PDF MC100LVEP210 MC100LVEP210 EP210 LVEP210 MC100LVEP210/D MC100 MC100EP210

    MC100E171

    Abstract: MC10E171 MC10E171FN
    Text: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to


    Original     		PDF MC10E171, MC100E171 MC10E/100E171 MC10E171/D MC100E171 MC10E171 MC10E171FN

    MC100E151

    Abstract: MC10E151 MC10E151FN
    Text: MC10E151, MC100E151 5V ECL 6-Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous


    Original     		PDF MC10E151, MC100E151 MC10E/100E151 MC10E151/D MC100E151 MC10E151 MC10E151FN