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    80960JA Price and Stock

    Intel Corporation TG80960JA3V25

    IC MPU I960 25MHZ 132QFP
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    DigiKey TG80960JA3V25 Tray 15 1
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    Intel Corporation NG80960JA3V33

    IC MPU I960 33MHZ 132QFP
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    DigiKey NG80960JA3V33 Bag 3 1
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    Intel Corporation NG80960JA25

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    Intel Corporation NG80960JA16

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    Intel Corporation TG80960JA25

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    80960JA Datasheets (11)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    80960JA Intel 3.3 V EMBEDDED 32-BIT MICROPROCESSOR Original PDF
    80960JA Intel Processor, EMBEDDED 32 Bit MICROPROCESSOR Original PDF
    80960JA Intel 3.3 V EMBEDDED 32-BIT MICROPROCESSOR Original PDF
    80960JA-16 Intel 3.3 V EMBEDDED 32-BIT MICROPROCESSOR Original PDF
    80960JA-16 Intel JX 3.3V Embedded 32-Bit Microprocessor Original PDF
    80960JA-1K Intel JX 3.3V Embedded 32-Bit Microprocessor Original PDF
    80960JA-25 Intel 3.3 V EMBEDDED 32-BIT MICROPROCESSOR Original PDF
    80960JA-25 Intel EMBEDDED 32-BIT MICROPROCESSOR Original PDF
    80960JA-2K Intel JX 3.3V Embedded 32-Bit Microprocessor Original PDF
    80960JA-33 Intel EMBEDDED 32-BIT MICROPROCESSOR Original PDF
    80960JA-92 Intel JX 3.3V Embedded 32-Bit Microprocessor Original PDF

    80960JA Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    80960JT

    Abstract: 80960JA 80960JD 80960JF instruction set processor intel 272852
    Text: Upgrading Designs from the 3.3 V, 5 V Tolerant 80960JA/JF/JD Embedded Processors to the 80960JT White Paper May 1998 Order Number: 273176-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual


    Original     		PDF 80960JA/JF/JD 80960JT 80960JT com/design/i960/swsup/ 80960JA 80960JD 80960JF instruction set processor intel 272852

    80960JA

    Abstract: AN1157 M29W002B M29W004B M29W004BB M29W004BT M29W008A
    Text: AN1157 APPLICATION NOTE Connecting the 80960JA Microcontroller to M29 Series Flash Memories CONTENTS • INTRODUCTION ■ ADVANTAGES OF FLASH ■ FLASH BUS ARCHITECTURE ■ 80960JA BUS ARCHITECTURE ■ TIMING REQUIREMENTS ■ CONCLUSION INTRODUCTION This application note describes a method to connect an


    Original     		PDF AN1157 80960JA M29W004B 512kb M29W002B, M29W008A AN1157 M29W002B M29W004BB M29W004BT

    TA80960KB-16

    Abstract: a8095925sv812 S80960SA16 ta80960kb-25 A80960KB-20 TA80960KB16 A8095925 a80960ca-25 a80960ca25 80385
    Text: 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet Product Features • ■ ■ ■ ■ Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 1x the Bus Clock for 80960JA/JF/JS


    Original     		PDF 80960JA/JF/JD/JS/JC/JT 32-Bit 80960Jx 80960JA/JF/JS 80960JD/JC 80960JT 80960JA 80960JF/JD TA80960KB-16 a8095925sv812 S80960SA16 ta80960kb-25 A80960KB-20 TA80960KB16 A8095925 a80960ca-25 a80960ca25 80385

    132 pin PGA socket

    Abstract: INTEL 132 QFP land pattern QFP 132 80960JA SF-QFJ132SA-G-02 Cobra
    Text: Relative orientations top views 0.100" typ. PGA A1 1.450" Pin 1 QFP Pin 1 ( TRST ) A1 Top view Target PCB 80960JA QFP Land Pattern 1.450" The Surface mount foot (QFP Base) is symmetrical and can solder to the Target PCB in any of 4 90° rotations. The PGA top,


    Original     		PDF 80960JA SF-QFJ132SA-G-02 FR4/G10 PC-PGA/QFP80960JA-G-01 PC-PGA/QFP-80960JA-G-01 132 pin PGA socket INTEL 132 QFP land pattern QFP 132 80960JA Cobra

    272495

    Abstract: FF30 272484 80960HX 80960HA
    Text: Converting Designs from the 80960HA/HD/HT Embedded Processors to the 80960JA/JF/JD/JT White Paper May 1998 Order Number: 273171-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual


    Original     		PDF 80960HA/HD/HT 80960JA/JF/JD/JT 80960JT LCD-960. 80960Hx 80960Jx com/design/i960/swsup/ 272495 FF30 272484 80960HA

    80960JD

    Abstract: 80960JT AD30
    Text: 80960JA/JF/JD/JT 3.3 V Microprocessor 1.0 Bus Functional Waveforms Figure 1 through Figure 6 illustrate typical 80960Jx bus transactions. Figure 7 depicts the bus arbitration sequence. Figure 8 illustrates the processor reset sequence from the time power is


    Original     		PDF 80960JA/JF/JD/JT 80960Jx 32-bit 80960JD 80960JT AD30

    80960SA reference

    Abstract: MARK AD9 80960JA 80960JD 80960JT intel packaging handbook 240800
    Text: 80960JA/JF/JD/JT 3.3 V EMBEDDED 32-BIT MICROPROCESSOR Advance Information Datasheet Product Features • ■ ■ ■ ■ Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture —One Instruction/Clock Execution —Core Clock Rate is:


    Original     		PDF 80960JA/JF/JD/JT 32-BIT 80960Jx 80960JA/JF 80960JD 80960JT --80960JA --80960JF/JD 80960SA reference MARK AD9 80960JA intel packaging handbook 240800

    80960JA

    Abstract: 80960JD 80960JT MCS 48
    Text: 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet Product Features • ■ ■ ■ ■ Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 1x the Bus Clock for 80960JA/JF/JS


    Original     		PDF 80960JA/JF/JD/JS/JC/JT 32-Bit 80960Jx 80960JA/JF/JS 80960JD/JC 80960JT 80960JA 80960JF/JD 80960JD 80960JT MCS 48

    80960JA

    Abstract: 80960JD 80960JF
    Text: 5 V 80960JA/JF/JD PROCESSOR CONVERSION TO 3.3 V White Paper May 1998 Order Number: 273172-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability


    Original     		PDF 80960JA/JF/JD 80960JA 80960JD 80960JF

    80960SA reference

    Abstract: b3 JF 80960JA 80960JD 80960JF
    Text: ADVANCE INFORMATION 80960JA/JF 3.3 V EMBEDDED 32-BIT MICROPROCESSOR • 3.3 V, 5.0 V Tolerant Version of the 80960JA/JF Processor • High Bandwidth Burst Bus Processors — 32-Bit Multiplexed Address/Data — Programmable Memory Configuration High-Performance Embedded Architecture


    Original     		PDF 80960JA/JF 32-BIT 80960JA/JF 80960JA 80960JF 80960SA reference b3 JF 80960JD

    NG80960JC-40

    Abstract: No abstract text available
    Text: 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet Product Features • ■ ■ ■ ■ Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 1x the Bus Clock for 80960JA/JF/JS


    Original     		PDF 80960JA/JF/JD/JS/JC/JT 32-Bit 80960Jx 80960JA/JF/JS 80960JD/JC 80960JT 80960JA 80960JF/JD NG80960JC-40

    132 pin PGA socket

    Abstract: 80960JA SF-QFJ132SA-L-01
    Text: Relative orientations top views 0.100" typ. PGA A1 1.450" Pin 1 QFP Pin 1 ( TRST ) Target PCB 80960JA QFP Land Pattern A1 Top view 1.450" 0.321" 1 2 The Surface mount foot (QFP Base) is symmetrical and can solder to the Target PCB in any of 4 90° rotations. The PGA top,


    Original     		PDF 80960JA SF-QFJ132SA-L-01 FR4/G10 100shell PC-PGA/QFP80960JA-L-01 PC-PGA/QFP-80960JA-L-01 132 pin PGA socket 80960JA

    4.Vout a9

    Abstract: Diode Mark N10 80960SA reference b3 JF clock generator in dual core processor m6 90 v-0 MARK AD9 microprocessor 32 bit 80960JA 80960JD
    Text: 80960JA/JF/JD/JT 3.3 V Embedded 32Bit Microprocessor Preliminary Datasheet Product Features • ■ ■ ■ ■ Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is:


    Original     		PDF 80960JA/JF/JD/JT 32Bit 80960Jx 80960JA/JF 80960JD 80960JT 32-Bit 80960JA 80960JF/JD 4.Vout a9 Diode Mark N10 80960SA reference b3 JF clock generator in dual core processor m6 90 v-0 MARK AD9 microprocessor 32 bit

    cpu microprocessor application

    Abstract: 80960JT 80960JA 80960JD 80960JF
    Text: 80960JA/JF/JD/JT 3.3 V Microprocessor 1.0 Device Identification: 80960Jx 3.3 V Processors 80960Jx processors may be identified electrically, according to device type and stepping see Figure 1, and Table 2 through Table 7 . Table 1 identifies the device type and stepping for all 5 V,


    Original     		PDF 80960JA/JF/JD/JT 80960Jx 80960Jx 32-bit 0000C 80960JA/JF 80960JA 80960JF cpu microprocessor application 80960JT 80960JD

    80960JA

    Abstract: 80960JD 80960JF A80L960JA intel packaging handbook 240800
    Text: A PRELIMINARY 80L960JA/JF 3.3 V EMBEDDED 32-BIT MICROPROCESSOR • ■ ■ ■ ■ ■ • 3.3 Volt Version of the 80960JA/JF Processor Pin/Code Compatible with all 80960Jx ■ High Bandwidth Burst Bus Processors — 32-Bit Multiplexed Address/Data — Programmable Memory Configuration


    Original     		PDF 80L960JA/JF 32-BIT 80960JA/JF 80960Jx 80L960JA/JF 80960JA 80960JD 80960JF A80L960JA intel packaging handbook 240800

    273109

    Abstract: No abstract text available
    Text: 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet Product Features • ■ ■ ■ ■ Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 1x the Bus Clock for 80960JA/JF/JS


    Original     		PDF 80960JA/JF/JD/JS/JC/JT 32-Bit 80960Jx 80960JA/JF/JS 80960JD/JC 80960JT 80960JA 80960JF/JD 273109

    Untitled

    Abstract: No abstract text available
    Text: P fö H y K ä M Ä G W in te i 80L960JA/JF 3.3V EMBEDDED 32-BIT MICROPROCESSOR 3.3 V Version o f the 80960JA/JF Processor Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model


    OCR Scan     		PDF 80L960JA/JF 32-BIT 80960JA/JF 80960Jx 80L960JA 80L960JF 80L960JF-

    intel CORE i3 instruction set

    Abstract: intel packaging handbook 240800
    Text: 80960JA/JF/JD/JT 3.3 V Embedded 32Bit Microprocessor Preliminary Datasheet Product Features • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 80960JA/JF lx the Bus Clock


    OCR Scan     		PDF 80960JA/JF/JD/JT 32Bit 80960Jx 80960JA/JF 80960JD 80960JT 32-Bit 80960JA 80960JF/JD intel CORE i3 instruction set intel packaging handbook 240800

    Untitled

    Abstract: No abstract text available
    Text: in te l 80960JA /JF EMBEDDED 32-BIT MICROPROCESSOR • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers 8


    OCR Scan     		PDF 80960JA 32-BIT 80960Jx 80960JA- 80960JF

    Untitled

    Abstract: No abstract text available
    Text: Advance Data Sheet September 1996 m icroelectronics group Lucent Technologies Bell Labs Inrxsvatians 960JX Embedded 32-Bit RISC Processor Features • Functionally equivalent to Inters 80960JA/JF embedded 32-bit microprocessor ■ High-performance embedded architecture


    OCR Scan     		PDF 960JX 32-Bit 80960JA/JF DS96-331ASIC 5002b

    i960 mc errata

    Abstract: intel packaging handbook 240800 TG80960JA-25 80960JT
    Text: 80960JA/JF/JD/JT 3.3 V EMBEDDED 32-BIT MICROPROCESSOR Advance Information Datasheet Product Features Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 80960JA/JF lx the Bus Clock


    OCR Scan     		PDF 80960JA/JF/JD/JT 32-BIT 80960Jx 80960JA/JF 80960JD 80960JT 80960JA 80960JF/JD i960 mc errata intel packaging handbook 240800 TG80960JA-25

    ltdo

    Abstract: No abstract text available
    Text: 80960JA/JF/JD/JT 3.3 V EMBEDDED 32-BIT MICROPROCESSOR Advance Information Datasheet P ro d u c t F e a tu re s • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is:


    OCR Scan     		PDF 80960JA/JF/JD/JT 32-BIT 80960Jx 80960JA/JF 80960JD 80960JT 80960JA 80960JF/JD ltdo

    LG VARIABLE FREQUENCY DRIVE is3

    Abstract: No abstract text available
    Text: intèi PRELIMINARY 80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR Pin/Cdde Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers 8 sets


    OCR Scan     		PDF 80960Jx 32-Bit 80960JA 80960JF-4 80960JA-1 80960JF 80960JA/JF 80960JA/JF LG VARIABLE FREQUENCY DRIVE is3

    Untitled

    Abstract: No abstract text available
    Text: 3.3 V 80960JA/JF 1.0 PURPOSE This docum ent contains inform ation for the 80960JA/JF microprocessor, including electrical characteristics and package pinout information. Detailed functional descriptions — other than para­ m etric perform ance — are published in the i96 P Jx


    OCR Scan     		PDF 80960JA/JF 80960JA/JF 80960Jx" 80960JA 80960JF 80960JD 80960JD 80960Jx