MAX2108
Abstract: TP2041 MAX105 MAX105ECS MAX107 TAD100
Text: 19-2006; Rev 0; 5/01 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX105 operates from a +5V analog supply and the LVDS output
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Original
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800Msps
MAX105
80-pin,
400Msps
MAX105,
MAX107
MAX105
MAX2108
TP2041
MAX105ECS
TAD100
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PDF
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Untitled
Abstract: No abstract text available
Text: ADS5402 www.ti.com SLAS936A – MARCH 2013 – REVISED AUGUST 2013 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES 1 • • • • • • • • • Dual Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp
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Original
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ADS5402
SLAS936A
12-Bit
800Msps
196-Pin
12x12mm)
ADS5402
ADS5401
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PDF
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L5A1
Abstract: No abstract text available
Text: ADS5401 www.ti.com SLAS946 – APRIL 2013 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES 1 • • • • • • • • • Single Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp
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Original
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ADS5401
SLAS946
12-Bit
800Msps
196-Pin
ADS5402
ADS5401
ADS5404
L5A1
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PDF
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Untitled
Abstract: No abstract text available
Text: ADS5402 www.ti.com SLAS936 – MARCH 2013 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES 1 • • • • • • • • • Dual Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp
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Original
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ADS5402
SLAS936
12-Bit
800Msps
196-Pin
12x12mm)
800Msps
ADS5401
|
PDF
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Untitled
Abstract: No abstract text available
Text: 19-2006; Rev 0; 5/01 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX105 operates from a +5V analog supply and the LVDS output
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Original
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800Msps
MAX105
80-pin,
400Msps
MAX105,
MAX107
MAX105
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PDF
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12x12mm BGA package thermal resistance
Abstract: DA5N
Text: ADS5402 www.ti.com SLAS939 – JANUARY 2013 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES 1 • Dual Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp Analog Input Buffer with High Impedance Input
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Original
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ADS5402
SLAS939
12-Bit
800Msps
196-Pin
12x12mm)
1020mW/ch
ADS5402
12x12mm BGA package thermal resistance
DA5N
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PDF
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12x12mm BGA package thermal resistance
Abstract: No abstract text available
Text: ADS5402 www.ti.com SLAS936 – MARCH 2013 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES 1 • • • • • • • • • Dual Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp
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Original
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ADS5402
SLAS936
12-Bit
800Msps
196-Pin
12x12mm)
ADS5402
ADS5401
12x12mm BGA package thermal resistance
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PDF
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MAX105
Abstract: MAX105ECS MAX107 MAX2108 Electrical signal Splitter 10g TAD100 differential encoding in qam 10dBm
Text: 19-2006; Rev 0; 5/01 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX105 operates from a +5V analog supply and the LVDS output
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Original
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800Msps
MAX105
80-pin,
400Msps
MAX105,
MAX107
MAX105
MAX105ECS
MAX2108
Electrical signal Splitter 10g
TAD100
differential encoding in qam
10dBm
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PDF
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Untitled
Abstract: No abstract text available
Text: ADS5402 www.ti.com SLAS936B – MARCH 2013 – REVISED JANUARY 2014 Dual 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5402 FEATURES DESCRIPTION • • • • • • • • The ADS5402 is a high linearity dual channel 12-bit, 800 Msps analog-to-digital converter ADC easing
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Original
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ADS5402
SLAS936B
12-Bit
800Msps
ADS5402
12-bit,
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PDF
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Electrical signal Splitter 10g
Abstract: No abstract text available
Text: 19-2006; Rev 0; 5/01 Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX105 operates from a +5V analog supply and the LVDS output
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Original
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800Msps
MAX105
200MHz,
400MHz,
MAX105EC
12x12x1
Electrical signal Splitter 10g
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PDF
|
Untitled
Abstract: No abstract text available
Text: ADS5401 www.ti.com SLAS946A – APRIL 2013 – REVISED JANUARY 2014 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES DESCRIPTION • • • • • • • • The ADS5401 is a high linearity single channel 12-bit, 800 Msps analog-to-digital converter ADC easing
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Original
|
ADS5401
SLAS946A
12-Bit
800Msps
ADS5401
12-bit,
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PDF
|
Untitled
Abstract: No abstract text available
Text: ADS5401 www.ti.com SLAS946 – APRIL 2013 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES 1 • • • • • • • • • Single Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp
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Original
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ADS5401
SLAS946
12-Bit
800Msps
196-Pin
800Msps
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ADS5401 www.ti.com SLAS946 – APRIL 2013 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES 1 • • • • • • • • • Single Channel 12-Bit Resolution Maximum Clock Rate: 800 Msps Low Swing Fullscale Input: 1.0 Vpp
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Original
|
ADS5401
SLAS946
12-Bit
800Msps
196-Pin
800Msps
|
PDF
|
Untitled
Abstract: No abstract text available
Text: ADS5401 www.ti.com SLAS946A – APRIL 2013 – REVISED JANUARY 2014 Single 12-Bit 800Msps Analog-to-Digital Converter Check for Samples: ADS5401 FEATURES DESCRIPTION • • • • • • • • The ADS5401 is a high linearity single channel 12-bit, 800 Msps analog-to-digital converter ADC easing
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Original
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ADS5401
SLAS946A
12-Bit
800Msps
ADS5401
12-bit,
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PDF
|
|
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GC5325
Abstract: TI6727
Text: GC5328 www.ti.com SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009 GC5328 Low-Power Wideband Digital Predistortion Transmit Processor Check for Samples: GC5328 FEATURES 1 • • • • • • • • Integrated DUC, CFR, and DPD Solution 20-MHz Max. Signal Bandwidth, Based on Max.
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Original
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GC5328
SLWS218A
GC5328
20-MHz
CDMA2000/TDSCDMA,
GC5328IZER
TMS320C6727
GC5325
TI6727
|
PDF
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lm317
Abstract: 14CLK 500MSPS ADC08D500 AN-450
Text: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。
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Original
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ADC08D500
ds201214
500MSPS
800MSPS
500MSPS
lm317
14CLK
ADC08D500
AN-450
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PDF
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Untitled
Abstract: No abstract text available
Text: Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DAC3283 SLAS693C – MARCH 2010 – REVISED MARCH 2015 DAC3283 Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter DAC 1 Features 3 Description • • The DAC3283 is a dual-channel 16-bit 800 MSPS
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Original
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DAC3283
SLAS693C
DAC3283
16-Bit,
16-bit
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PDF
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GC5325
Abstract: No abstract text available
Text: GC5328 www.ti.com SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009 GC5328 Low-Power Wideband Digital Predistortion Transmit Processor Check for Samples: GC5328 FEATURES 1 • • • • • • • • Integrated DUC, CFR, and DPD Solution 20-MHz Max. Signal Bandwidth, Based on Max.
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Original
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GC5328
SLWS218A
GC5328
20-MHz
CDMA2000/TDSCDMA,
GC5328IZER
TMS320C6727
GC5325
|
PDF
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SDR FPGA adc
Abstract: TXB17 lte20 free TMS320C6748 adaptive algorithm dpd GC533x DPD Application Note
Text: GC5330 GC5337 Preliminary www.ti.com SLWS226 A – DECEMBER 2010 – REVISED DECEMBER 2010 Wideband Transmit-Receive Digital Signal Processors Check for Samples: GC5330, GC5337 (Preliminary) FEATURES APPLICATIONS • • • • • • • • 1 • •
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Original
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GC5330
GC5337
SLWS226
GC5330,
62-MHz
SDR FPGA adc
TXB17
lte20
free TMS320C6748
adaptive algorithm dpd
GC533x DPD Application Note
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PDF
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LTE MIMO repeater
Abstract: SDR FPGA adc rxa12 adaptive algorithm dpd
Text: GC5330 GC5337 SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com Wideband Transmit-Receive Digital Signal Processors Check for Samples: GC5330, GC5337 FEATURES APPLICATIONS • • • • • • • • 1 • • • • • • • • •
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Original
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GC5330
GC5337
SLWS226
GC5330,
62-MHz
LTE MIMO repeater
SDR FPGA adc
rxa12
adaptive algorithm dpd
|
PDF
|
Untitled
Abstract: No abstract text available
Text: DAC3283 www.ti.com SLAS693A – MARCH 2010 – REVISED APRIL 2010 Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter DAC Check for Samples: DAC3283 FEATURES APPLICATIONS • • • • • • 1 • • • • • • • • • • • Dual, 16-Bit, 800 MSPS DACs
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Original
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DAC3283
SLAS693A
16-Bit,
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PDF
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12x12mm BGA package thermal resistance
Abstract: fpga radar Analog Filter design
Text: ADS5404 www.ti.com SLAS945 – APRIL 2013 Dual Channel 12-Bit 500Msps Analog-to-Digital Converter Check for Samples: ADS5404 FEATURES 1 • • • • • • • • • • • Dual Channel 12-Bit Resolution Maximum Clock Rate: 500 Msps Low Swing Fullscale Input: 1.0 Vpp
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Original
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ADS5404
SLAS945
12-Bit
500Msps
196-Pin
12x12mm)
12x12mm BGA package thermal resistance
fpga radar
Analog Filter design
|
PDF
|
IEEE-1596
Abstract: E5430 R161 022 BAV99ZXCT LC1210 AD9734 AD9735 AD9736 AVDD33 esd p3
Text: 10-/12-/14-Bit, 1200 MSPS DACS AD9734/AD9735/AD9736 FEATURES FUNCTIONAL BLOCK DIAGRAM RESET A reduced-specification LVDS interface is utilized to achieve the high sample rate. The output current can be programmed over a range of 8.66 mA to 31.66 mA. The AD973x family is
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Original
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10-/12-/14-Bit,
AD9734/AD9735/AD9736
AD973x
160-lead
10-BIT
BC-160-1
IEEE-1596
E5430
R161 022
BAV99ZXCT
LC1210
AD9734
AD9735
AD9736
AVDD33
esd p3
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PDF
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verilog code to generate sine wave
Abstract: open LVDS deserialization IP verilog code for sine wave using FPGA 0x0000011 C71B MB86064 fujitsu lvds standard BF15 D132 LVDS17
Text: High-Speed Data Interface for Stratix Devices & Fujitsu MB86064 DACs Application Note AN-316-1.0 Introduction Implementing the digital interface to drive a high-speed digital-toanalogue converter DAC is challenging. The conversion rates of highspeed DACs has increased significantly in recent years, so special design
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Original
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MB86064
AN-316-1
14-bit
verilog code to generate sine wave
open LVDS deserialization IP
verilog code for sine wave using FPGA
0x0000011
C71B
fujitsu lvds standard
BF15
D132
LVDS17
|
PDF
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