DS2165Q
Abstract: No abstract text available
Text: D A LLA S s e m ic o n d u c to r DS2165/DS2165Q 16/24/32Kbps ADPCM Processor PIN ASSIGNM ENT FEATURES • Compresses/expands 64Kbps PCM voice to/from either 32Kbps, 24Kbps, or 16Kbps • Dual, fully independent channel architecture; device can be programmed to perform either:
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16/24/32Kbps
64Kbps
32Kbps,
24Kbps,
16Kbps
DS2165
DS2165Q
28-PIN
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Untitled
Abstract: No abstract text available
Text: DS2164Q DALLAS SEMICONDUCTOR DS2164Q G.726 ADPCM Processor FEATURES PIN ASSIGNMENT • Compresses/expands 64Kbps PCM voice to/from either 32Kbps, 24Kbps, or 16Kbps as per the CCITT/ ITU G.726 specification T- o *Q £ 5 5 B 1 U Ü Î _i I—I—ICC Z > >- O
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DS2164Q
64Kbps
32Kbps,
24Kbps,
16Kbps
XT/77X
l413D
777777777T
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TC55V2325FF-7
Abstract: TC55V2325FF 0818 ci
Text: TO SH IB A TC55V2325FF-7 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT TENTATIVE SILICON GATE CMOS 65,536-WORD BY 32-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM DESCRIPTION The TC55V2325FF is a 2,097,152-bit synchronous pipelined burst static random access memory SRAM
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TC55V2325FF-7
TC55V2325FF
152-bit
LQFP100-P-1420-0
TC55V2325FF-7
0818 ci
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KM44S4020AT10
Abstract: KM44S4020A
Text: PRELIMINARY KM44S4020A 4M X CMOS SDRAM 4 BIT SYNCHRONOUS DYNAMIC RAM GENERAL DESCRIPTION FEATURES - JEDEC standard 3.3V power supply. - LVTTL compatible with multiplexed address. - Dual bank / Pulse ftAS. - WCBR cycle with address key programs. • Latency Access from column address
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KM44S4020A
KM44S4020A
G02054b
KM44S4020AT10
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W777
Abstract: electronica ddr
Text: H M 5 2 1 6 8 0 5 Preliminary S e r ie s 1,048,575-word x 8-bit x 2-bank Synchronous Dynamic RAM HITACHI All Inputs and outputs are referred to the rising edge of tbe clock input. The HM5216805 is offered in 2 banks for improved performance. Features •3J V Power supply
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575-word
HM5216805
HM5218805TT-10
HM52ieaonr-i2
HM5218B06TT-15
TTP-440E)
Hz/83
Hz/66
695/DDR/MFM
M19TD4S
W777
electronica ddr
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