IR 30 D1

Contextual Info: SN74ALS236 64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107A-OCTOBER 1986 - REVISED SEPTEMBER 1993 Asynchronous Operation Organized as 64 Words by 4 Bits DW OR N PACKAGE TOP VIEW r NC [ 1 Data Rates From 0 to 30 MHz 3-State Outputs 16 J VCC 15 ] S O

Contextual Info: sse • d flui?a3 ODflbiflfl t SNS4HC4066, TLC4066I SILICQN-GATE CMOS QUADRUPLE BILATERAL ANALOG SWITCH TEXAS INSTR LOGIC 02922, JANUARY 1988 High Degree of Linearity SN64HC4066 . . . J OR N PACKAGE T L C 40 66 I. . . D OR N PACKAG E • High On-Off Output Voltage Ratio

MIL-STD-463

Abstract: LM136-2.5
Contextual Info: LT1009, LT1009Y 2.5-V INTEGRATED REFERENCE CIRCUITS SLVS013E - MAY 1987 - REVISED AUGUST 1995 • • • • • • Excellent Temperature Stability Initial Tolerance. . . 0.2% Max

24-042

Abstract: applications of microprocessor in printer TL16C450 TL16C451 TL16C452
Contextual Info: TL16C451, TL16C452 ASYNCHRONOUS COMMUNICATIONS ELEMENTS SLLS053A- D3284, MAY 1989 - REVISED JANUARY 1990 Fully Programmable Serial Interface Characteristics: 5-, 6-, 7-, or 8-Bit Characters Even-, Odd-, or No-Parity Bit Generation and Detection 1-, 1 1/2-, or 2 Stop-Bit Generation

KVT 20 Temperature

Abstract: SN54ABTH182504A SN54ABTH18504A SN74ABTH182504A SN74ABTH18504A
Contextual Info: SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS - S C B S 1 6 5 A - AU G U S T 1993 - REVISED AU G U S T 1994 ' Members of the Texas Instruments

SN74ALVCH16374

Contextual Info: SN74ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021 -JU L Y 1995 DGG OR DL PACKAGE {TOP VIEW Member of the Texas Instruments Widebus Family EPIC™ Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per

74AC16374

Abstract: 4a53
Contextual Info: 74AC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS123A- P3470, MARCH 1 9 9 0 - REVISED APRIL 1993 logic diagram positive logic logic sym b o lt 1EN 10E 48 1CLK 24 20Ë 25 2CLK 47 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 201 2D2 203 2D4 2D5

HC686

Abstract: G1.L SN54HC682 SN54HC684 SN74HC682 SN74HC684 hc682
Contextual Info: TYPES SN54HC682, SN54HC684, SN54HC686 SN74HC682, SN74HC684, SN74HC686 8 BIT MAGNITUDE COMPARATORS HIGH-SPEED CMOS LOGIC D 2 8 0 4 , M AR C H 1 9 8 4 S N 5 4 H C 6 8 2 , S N 5 4 H C 6 8 4 . . . J PACKAGE S N 7 4 H C 6 8 2 . S N 5 4 H C 6 8 4 . . J OR N PACKAGE

SN74ABT3611

Abstract: mdv 434
Contextual Info: SN74ABT3611 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SC B S 127C - JULY 1992 - RE V IS E D A P R IL 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Empty Flag EF and Almost-Empty Flag (AE) Synchronized by CLKB 64 x 36 Clocked FIFO Buffering Data From

SN751177

Abstract: 11A1 RS-422-A SN751177NSLE SN751178 QDT1114 D3381
Contextual Info: 1%11„ SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS _ S L L S 0 5 9 A - D3381, FEBRUARY 1 9 9 0 -R E V IS E D JANUARY 1993 Meets EIA Standards RS-422-A, RS485 SN751177 — N PACKAGE TOP VIEW Meets CCITT Recommendations V.10, V 11 X.26, X.27

D1314

Abstract: SN75361 207B SN75107A SN75107B SN75207 SN75207B SN55109A
Contextual Info: SN75207, SN75207B DUAL SENSE AMPLIFIER FOR MOS MEMORIES OR DUAL HIGH-SENSITIVITY LINE RECEIVERS S LLS Q 69A - D1314, JULY 1973 - REVISED JANUARY 1993 □ O R N PACKAGE TO P V IE W Plug-In Replacement for SN75107A and SN75107B With Improved Characteristics

k54c

Abstract: FD19 TL16PNP550A
Contextual Info: TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUG AND PLAY PnP AND AUTO-FLOW CONTROL SLLS190A- MARCH 1995 -REVISED MAY 1995 PnP Card Auto-Conflguratlon Sequence Compliant External Pin-to-Bypass PnP Auto-Conflguratlon Sequence In UART Bypass Mode, the Stand Alone

Contextual Info: TEXAS INSTR LOGIC 25E O • flclt.l72'3 Q0flL7flfl 2 ■ SN54HC533, SN74HCS33 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS D2S84, DECEMBER I9 8 2 -R E V IS E 0 SEPTEMBER 1307 SNB4HC533 . . . J PACKAGE SN74HC633 . . . D W O R N PACKAGE 8 Latches in a Single Package

d2544

Abstract: LS356 SN54LS354 SN54LS355 SN54LS356 SN74LS354 SN74LS355 SN74LS356 SN74LS35 909d
Contextual Info: S N 5 4 L S 3 5 4 , S N 5 4 L S 3 5 5 , S N 54L S 356 S N 7 4 L S 3 5 4 , S N 7 4 L S 3 5 5 , S N 74L S 356 8-LINE TO M IN E DATA SELECTORSIMULTIPLEXERS/REGISTERS SD LS164 0 2 5 4 4 , JULY 1979 —REVISED MARCH 1968 • Transparent Latches on Data Select Inputs

SN74LVT652

Contextual Info: SN74LVT652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS FEBRUARY 1992 PACKAGE PINOUT TOP VIEW Supports Mixed-Mode Signal Operation; 5 V Input and Output Voltages With 3.3 V Vcc ( • Supports Unregulated Battery Operation Down to 2.7 V • State-of-the-Art BICMOS Design for 3.3 V

TCM2912

Abstract: TCM29C14A TCM2911 TCM129C13A TCM129C14A TCM129C16A TCM129C17A TCM2910A TCM2911A TCM29C13A
Contextual Info: TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A COMBINED SINGLE-CHIP PCM CODEC AND FILTER S CTS030D - A UG UST 1989 - REVISED JULY 1996 Replace Use of TCM2910A and TCM2911A in Tandem With TCM2912B/C FE A TU R E S TA B LE

SLLS008C-D2S31

Abstract: SN75ALS193 d2931 AM26LS32A RS-422-A SN75ALS197
Contextual Info: SN75ALS193 QUAD DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS ^ * * * * * * * * * * * _ SLLS008C - D2931, JUNE 1986 - REVISED MARCH 1993 Meets EIA Standards RS-422-A and RS-423-A SN75ALS193 . . . J P A C K A G E t TOP VIEW

Contextual Info: 54ACT11652, 74ACT11652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS S CAS 087 - D 3106, APRIL 1993 Bus Transceivers/Registers 54A C T11652. . . JT PACKAGE 74ACT11652 . . . DW PACKAGE Independent Registers and Enables for A and B Buses TOP VIEW

Contextual Info: SN74ALS29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER SDAS118C - FEBRUARY 1987 - REVISED JANUARY 1995 Functionally Similar to AMD's AM29854 High-Speed Bus Transceiver With Parity Generator/Checker Parlty-Error Flag With Open-Collector Outputs Latch for Storing the Parlty-Error Flag

D3964

Abstract: TLE2144I
Contextual Info: TLE2144, TLE2144A,TLE2144Y EXCALIBUR LOW-NOISE HIGH-SPEED PRECISION QUAD OPERATIONAL AMPLIFIERS D3964, N O VEM BER 1991 a v a ila b le fe a t u r e s Low Noise: 10 Hz 1 kHz Low Vio . . . 1.5 mV Max at 25°C 15 nV/Vflz 10.5 nV/VHz Single or Split Supply . . . 4 V to 44 V

Contextual Info: SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS ^ _ SDAS125B - M ARCH 1984 - REVISED DECEMBER 1994 • Fully Synchronous Operation for Counting and Programming • Internal Carry Look-Ahead Circuitry for

Contextual Info: SN54AS194, SN74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS SDAS212A - DE CE M B E R 1983 - RE V IS E D DECEM BER 1994 Parallel-to-Serlal, Serial-to-Parallel Conversions Left or Right Shifts Parallel Synchronous Loading Direct Overriding Clear Temporary Data-Latchlng Capability

Contextual Info: SN54ABT8996, SN74ABT8996 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS SCBS489 -AU GU ST 1994 * * * SN54ABT8996. JT PACKAGE SN74ABT8996. DB OR DW PACKAGE (TOP VIEW) A4[ A3 [ A2[ A1[ A0[ BYP [ GND [ PTDO [ PTCK[

Contextual Info: SN74AS195 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER SDAS138B-DECEMBER 1983 - REVISED JANUARY 1995 Parallel-to-Serlai, Serlal-to-Parallel Conversions Parallel Synchronous Loading J and K Inputs to First Stage Right Shift Only With Complementary Outputs on Last Stage