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    74LV10 Search Results

    74LV10 Result Highlights (5)

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    74LV10ATELL-E Renesas Electronics Corporation HD74LV-A Series Visit Renesas Electronics Corporation
    74LV10AFPEL-E Renesas Electronics Corporation HD74LV-A Series Visit Renesas Electronics Corporation
    SN74LV10ANSR Texas Instruments Triple 3-Input Positive-NAND Gate 14-SO -40 to 85 Visit Texas Instruments Buy
    SN74LV10ADRG4 Texas Instruments Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 85 Visit Texas Instruments Buy
    SN74LV10AD Texas Instruments Triple 3-Input Positive-NAND Gate 14-SOIC -40 to 85 Visit Texas Instruments Buy
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    74LV10 Price and Stock

    Rochester Electronics LLC SN74LV10AD

    IC GATE NAND 3CH 3-INP 14SOIC
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    IC GATE NAND 3CH 3-INP 14SOIC
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    Rochester Electronics LLC SN74LV10APW

    IC GATE NAND 3CH 3-INP 14TSSOP
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    Rochester Electronics LLC SN74LV10ADGVR

    IC GATE NAND 3CH 3-INP 14TVSOP
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    Texas Instruments SN74LV10ADR

    IC GATE NAND 3CH 3-INP 14SOIC
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    Rochester Electronics SN74LV10ADR 2,500 1
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    Find more 74LV10 price and stock on Findchips.com

    74LV10 Datasheets (84)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LV10 Philips Semiconductors Triple 3-input NAND gate Original PDF
    74LV107 Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Original PDF
    74LV107D Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74LV107D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74LV107D Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF
    74LV107D Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF
    74LV107D Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF
    74LV107D Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF
    74LV107DB Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74LV107DB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74LV107DB Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF
    74LV107DB Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF
    74LV107DB Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF
    74LV107DB Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF
    74LV107DB-T Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74LV107D-T Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74LV107N Philips Semiconductors Dual JK flip-flop with reset negative-edge trigger Original PDF
    74LV107N Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74LV107N Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF
    74LV107N Philips Semiconductors Dual JK flip-flop with reset, negative-edge trigger Scan PDF

    74LV10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LV10

    Abstract: 74LV10PW
    Text: INTEGRATED CIRCUITS 74LV10 Triple 3-input NAND gate Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 FEATURES DESCRIPTION


    Original     		PDF 74LV10 74LV10 74HC/HCT10. 74LV10PW

    nsd 102

    Abstract: 74LV109 74LV109PW
    Text: INTEGRATED CIRCUITS 74LV109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger


    Original     		PDF 74LV109 74LV109 74HC/HCT109. nsd 102 74LV109PW

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS 74LV107 Dual JK flip-flop with reset; negative-edge trigger Product specification IC24 Data Handbook Philips Semiconductors 1997 Feb 03 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger FEATURES


    Original     		PDF 74LV107 74LV107

    74LV107

    Abstract: 74LV107PW
    Text: INTEGRATED CIRCUITS 74LV107 Dual JK flip-flop with reset; negative-edge trigger Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger


    Original     		PDF 74LV107 74LV107 74HC/HCT107. 74LV107PW

    74LV10

    Abstract: 74LV10D
    Text: INTEGRATED CIRCUITS 74LV10 Triple 3-input NAND gate Product data Supersedes data of 1998 Apr 20 Philips Semiconductors 2003 Mar 04 Philips Semiconductors Product data Triple 3-input NAND gate 74LV10 FEATURES DESCRIPTION • Optimized for Low Voltage applications: 1.0 V to 3.6 V


    Original     		PDF 74LV10 74LV10 74HC/HCT10. 74LV10D

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS 74LV10 Triple 3-input NAND gate Product data Supersedes data of 1998 Apr 20 Philips Semiconductors 2003 Mar 04 Philips Semiconductors Product data Triple 3-input NAND gate 74LV10 FEATURES DESCRIPTION • Optimized for Low Voltage applications: 1.0 V to 3.6 V


    Original     		PDF 74LV10 74LV10

    Untitled

    Abstract: No abstract text available
    Text: SN54LV10A, 74LV10A TRIPLE 3ĆINPUT POSITIVEĆNAND GATE SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV10A, SN74LV10A SCES338E SN54LV10A SN74LV10A LV10A

    Untitled

    Abstract: No abstract text available
    Text: SN54LV10A, 74LV10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCES338B – SEPTEMBER 2000 – REVISED DECEMBER 2000 D D D D SN54LV10A . . . J OR W PACKAGE 74LV10A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)


    Original     		PDF SN54LV10A, SN74LV10A SCES338B 000-V A114-A) A115-A) SN54LV10A SN74LV10A

    5555 FAIRCHILD optocoupler

    Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
    Text: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference


    Original     		PDF SCYB017A A010203 5555 FAIRCHILD optocoupler MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N

    Untitled

    Abstract: No abstract text available
    Text: SN54LV10A, 74LV10A TRIPLE 3ĆINPUT POSITIVEĆNAND GATE SCES338E − SEPTEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN54LV10A, SN74LV10A SCES338E SN54LV10A SN74LV10A LV10A

    dual jk flipflop

    Abstract: 74LV107 74LV107PW MS-012AB
    Text: Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74LV107 FEATURES DESCRIPTION • W id e o p e ra tin g : 1.0 to 5.5 V T h e 74 L V 1 0 7 is a lo w -v o lta g e S i-g a te C M O S d e v ic e th a t is pin a n d


    OCR Scan     		PDF 74LV107 SQT402-1 MO-153 dual jk flipflop 74LV107 74LV107PW MS-012AB

    74LV10

    Abstract: 74LV10PW
    Text: Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 FEATURES DESCRIPTION • Optim ized for Low Voltage applications: 1.0 to 3.6 V The 74LV10 is a l°w -voltage Si-gate CMOS device and is pin and function com patible with 74H C /H C T10.


    OCR Scan     		PDF 74LV10 SQT402-1 MO-153 74LV10 74LV10PW

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS [M m S P I E 74LV107 Dual JK flip-flop with reset; negative-edge trigger Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 PHILIPS Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger


    OCR Scan     		PDF 74LV107 74LV107

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS 74LV10 Triple 3-input NAND gate Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 PHILIPS Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 FEATURES DESCRIPTION


    OCR Scan     		PDF 74LV10 74LV10 74HC/HCT10.

    74LV10

    Abstract: 74LV10PW
    Text: Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 FEATURES DESCRIPTION • W ide operating voltage 1 0 to 5 5 V The 74LV10 is a iow-voitage Si-gate CMOS device and is pin and function com patible with 74H C /H C T10. • Optim ized for Low Voltage applications: 1.0 to 3.6 V


    OCR Scan     		PDF 74LV10 SQT402-1 MO-153 74LV10 74LV10PW

    Untitled

    Abstract: No abstract text available
    Text: Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LV109 FEATURES DESCRIPTION • Optimized for low voltage applications: 1.0 to 3.6 V The 74LV109 is a low-voltage Si-gate CMOS device that is pin and


    OCR Scan     		PDF 74LV109 74LV109 74HC/HCT109.

    74LV107

    Abstract: 74LV107PW MS-012AB
    Text: Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74LV107 FEATURES DESCRIPTION • W ide operating: 1.0 to 5.5 V The 74LV107 is a low-voltage Si-gate CM OS device that is pin and function com patible with 74H C /H C T107.


    OCR Scan     		PDF 74LV107 SQT402-1 MO-153 74LV107 74LV107PW MS-012AB

    74LV109

    Abstract: MS-012AC SSOP16
    Text: This Material Copyrighted By Its Respective Manufacturer P hilips S e m ic o n d u c to rs P ro d u ct sp e cifica tio n Dual JK flip-flop with set and reset; positive-edge trigger LOGIC SYMBOL IEEE/IEC 74LV109 FUNCTIONAL DIAGRAM Sd J Q CP FF1 •K Q Rd


    OCR Scan     		PDF 74LV109 SV00S18 SQT403-1 MO-153 74LV109 MS-012AC SSOP16

    Untitled

    Abstract: No abstract text available
    Text: Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74LV107 FEATURES DESCRIPTION • Wide operating: 1.0 to 5.5 V The 74LV107 is a iow-voitage Si-gate CMOS device that is pin and function compatible with 74HC/HCT1G7.


    OCR Scan     		PDF 74LV107 74LV107 74HC/HCT1G7.

    74LV10

    Abstract: 74LV10D 74LV10DB 74LV10PW
    Text: Product Specification Philips Semiconductors 74LV10 Triple 3-input NAND gate QUICK REFERENCE DATA FEATURES GND = 0 V; Tamb = 25°C; tr = t, < 2.5 ns • • • • • • Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between Vcc = 2.7 V and


    OCR Scan     		PDF 74LV10 74LV10 74HC/HCT10. 7110flSb 74LV10D 74LV10DB 74LV10PW

    Untitled

    Abstract: No abstract text available
    Text: Phifips Semiconductors Product specification Triple 3-input NAND gate 74LV10 FEATURES DESCRIPTION • Optimized for Low Voltage applications: 1.0 to 3.6 V The 74L.V10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10.


    OCR Scan     		PDF 74LV10 74HC/HCT10. 74LV10

    DIL 14 M

    Abstract: 74LV10 74LV10D 74LV10DB 74LV10N 74LV10PW
    Text: Philips Semiconductors Product Specification Triple 3-input NAND gate FEATURES • • • • • • 74LV10 QUICK REFERENCE DATA GND = 0 V; T „ * = 25°C; t, = t, S 2.5 ns Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between Vcc = 2.7 V and


    OCR Scan     		PDF 74LV10 74LV10 74HC/HCT10. 711Dfl2fc. DIL 14 M 74LV10D 74LV10DB 74LV10N 74LV10PW

    74LV109

    Abstract: 74LV109D 74LV109DB 74LV109N 74LV109PW Philips 74hc Logic Family specifications
    Text: Product Specification Philips Semiconductors Dual JK flip-flop with set and reset; positive-edge trigger 74LV109 QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; t, = t, < 2.5 ns FEATURES Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels


    OCR Scan     		PDF 74LV109 74LV109 74HC/HCT109. 74LV109D 74LV109DB 74LV109N 74LV109PW Philips 74hc Logic Family specifications

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS 74LV109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 PHILIPS Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger


    OCR Scan     		PDF 74LV109 74LV109