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    74LS37 Search Results

    74LS37 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74LS373PA-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS374P-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS373P-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS373FPEL-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
    74LS37FPEL-E Renesas Electronics Corporation HD74LS Series Visit Renesas Electronics Corporation
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    74LS37 Price and Stock

    Texas Instruments SN74LS373DWR

    IC D-TYPE TRANSP SGL 8:8 20SOIC
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    DigiKey SN74LS373DWR Digi-Reel 4,707 1
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    Mouser Electronics SN74LS373DWR 6,727
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    Ameya Holding Limited SN74LS373DWR 2,850
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    Texas Instruments SN74LS374NSR

    IC FF D-TYPE SNGL 8BIT 20SO
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    DigiKey SN74LS374NSR Cut Tape 2,595 1
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    SN74LS374NSR Digi-Reel 2,595 1
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    Mouser Electronics SN74LS374NSR 9,296
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    Rochester Electronics SN74LS374NSR 2,840 1
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    Win Source Electronics SN74LS374NSR 4,000
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    Texas Instruments SN74LS373NSR

    IC D-TYPE TRANSP SGL 8:8 20SO
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    DigiKey SN74LS373NSR Digi-Reel 2,313 1
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    SN74LS373NSR Cut Tape 2,313 1
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    SN74LS373NSR Reel 2,000 2,000
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    Mouser Electronics SN74LS373NSR 1,721
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    Rochester Electronics SN74LS373NSR 18,540 1
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    Chip 1 Exchange SN74LS373NSR 42
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    Chip One Stop SN74LS373NSR Cut Tape 1,132
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    Win Source Electronics SN74LS373NSR 36,500
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    Texas Instruments SN74LS377DWR

    IC FF D-TYPE SNGL 8BIT 20SOIC
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    DigiKey SN74LS377DWR Cut Tape 1,995 1
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    Mouser Electronics SN74LS377DWR 2,151
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    Texas Instruments SN74LS374DW

    IC FF D-TYPE SNGL 8BIT 20SOIC
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    DigiKey SN74LS374DW Tube 664 1
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    TME SN74LS374DW 174 1
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    Win Source Electronics SN74LS374DW 4,000
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    74LS37 Datasheets (70)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LS37 Fairchild Semiconductor 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Original PDF
    74LS37 Hitachi Semiconductor Quadruple 2-input Positive NAND Buffers Original PDF
    74LS37 National Semiconductor TRI-STATEE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Original PDF
    74LS37 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS Original PDF
    74LS37 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS37 Raytheon NOR, NAND Buffers Scan PDF
    74LS37 Signetics Quad Two-Input NAND Buffer Scan PDF
    74LS37 Signetics Quad 2-Input NAND Buffer Scan PDF
    74LS37 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS373 Fairchild Semiconductor 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Original PDF
    74LS373 Fairchild Semiconductor 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Original PDF
    74LS373 Hitachi Semiconductor Octal D-type Transparent Latches(with three-state outputs) Original PDF
    74LS373 Motorola OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS, OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT Original PDF
    74LS373 National Semiconductor TRI-STATEE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops Original PDF
    74LS373 On Semiconductor LOW POWER SCHOTTKY Original PDF
    74LS373 Texas Instruments OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS Original PDF
    74LS373 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS373 Signetics Latches / Flip-Flops Scan PDF
    74LS373 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS373DC Fairchild Semiconductor Octal Transparent Latch Scan PDF

    74LS37 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    ls378

    Abstract: 74LS377 74LS174 74LS175 74LS378 74LS379
    Text: SN54/74LS377 SN54/74LS378 SN54/74LS379 OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a


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    SN54/74LS377 SN54/74LS378 SN54/74LS379 74LS377 74LS378 74LS174, 74LS379 74LS175 74LS379 ls378 74LS174 PDF

    74ls37

    Abstract: 74LS37 TRUTH TABLE 751A-02
    Text: SN54/74LS37 QUAD 2-INPUT NAND BUFFER QUAD 2-INPUT NAND BUFFER VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN


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    SN54/74LS37 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD 74ls37 74LS37 TRUTH TABLE 751A-02 PDF

    74LS374 74LS373 74ls373

    Abstract: 74LS373 74LS373 40 pin 74LS374 pin diagram 74ls373 LOGIC OF 74LS373 74LS374 DATASHEET 8D213 LS373 SN54LSXXXJ
    Text: SN54/74LS373 SN54/74LS374 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus


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    SN54/74LS373 SN54/74LS374 74LS373 74LS374 74LS374 74LS373 74ls373 74LS373 40 pin pin diagram 74ls373 LOGIC OF 74LS373 74LS374 DATASHEET 8D213 LS373 SN54LSXXXJ PDF

    74LS377

    Abstract: 74ls175 pin diagram 74LS174 74LS175 74LS378 74LS379 motorola ceramic dual in-line case 74ls377 motorola
    Text: SN54/74LS377 SN54/74LS378 SN54/74LS379 OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a


    Original
    SN54/74LS377 SN54/74LS378 SN54/74LS379 74LS377 74LS378 74LS174, 74LS379 74LS175 74ls175 pin diagram 74LS174 motorola ceramic dual in-line case 74ls377 motorola PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LS377 S ignetics Flip-Flop Octal D Flip-Flop With Clock Enable Product Specification Logic Products FEATURES • Ideal for addressable register applications • Clock Enable for address and data synchronization applications • Eight edge-triggered D flip-flops


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    74LS377 20-pin 40MHz SQL-20 500ns 500ns PDF

    54LS378DM

    Abstract: 54LS378FM 74LS378DC 74LS378FC 74LS378PC 6bit register
    Text: 378 C O N N E C T IO N D IA G R A M P IN O U T A / / • b ^ V 54LS/74LS378 P A R A L LE L D REGISTER \ With Enable 1 TjOvcc iE QoE Ï Do [3 Ü lD s s ]Q 5 D i[4 là ] 04 Q i[| T 2I Q d2 [| îï] “3 0 2 |T ÏÔ ]0 3 GNO [ T J }C P D E S C R IP T IO N — T h e ’378 is a 6 -b it reg iste r w ith a b u ffe re d co m m o n enable.


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    54LS/74LS378 54/74LS 54LS378DM 54LS378FM 74LS378DC 74LS378FC 74LS378PC 6bit register PDF

    74L8138

    Abstract: SC80C451 read/74L8138
    Text: ’four Choice 87C51 OTP » » m m rn rn or Introducing W SI’s New P S D 211R Programmable Microcontroller Peripheral for Cost Sensitive Applications Replace all this. PLD/LOGIC 1 GV, Z O V 8 , Z 2 V 1 0 , etc. Your Low Cost MCU 80C31 G8HC11 74LS373 74L8138/PLD


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    87C51 80C31 G8HC11 74LS373 74L8138/PLD 74LS374 74L8374 PSB211R PSD211R PEP300 74L8138 SC80C451 read/74L8138 PDF

    D Flip Flops

    Abstract: 74ls175 pin diagram 74ls376 4LS08 74LS175 LS08 AM2919 CD0017
    Text: 80S~ISZUJV/Z0S~ISZU1V A m 25LS 07/A m 25LS08 Hex/Q uad Parallel D Registers with Register Enable DISTINCTIVE CHARACTERISTICS • • • • 4-bit and 6-bit parallel registers Com m on Clock and Common Enable Positive edge triggered D flip flops Second sourced by Tl as 54LS/74LS37B and 379


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    Am25LS07/Am25LS08 54LS/74LS37B Am25LS 0-45v Am25LS07 Am25LS08 Am54LS/74LS174 Am54LS/ 74LS175 Am25LS D Flip Flops 74ls175 pin diagram 74ls376 4LS08 LS08 AM2919 CD0017 PDF

    D flip-flop 74175 pin

    Abstract: 74LS78 74LS374 74ls373 93L38 74298 D150 D190 74LS374 74LS373 74ls373 D Flip-Flop
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 Vcc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| FI j j j SD SD J Q J C CP Q — e CP K >— 12 Q Q 5— 9 K CD CD LlI lil LiJ Lil LiTIU LzJ LlI üü bsJ QNO 9 3 4 li 5 D85 54LS/74LS373


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    54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 /74LS573 93L34 D flip-flop 74175 pin 74LS78 74LS374 74ls373 93L38 74298 D150 D190 74LS374 74LS373 74ls373 D Flip-Flop PDF

    BA335

    Abstract: No abstract text available
    Text: 379 CONNECTION DIAGRAM PINOUT A /54LS/74LS379 h u^> QUAD PARALLEL REGISTER *[I is]V c c With Enable Oo(T Ts 1q 3 Oo [T 03 oo [T ÏU D3 D([T «JO z Oi [ ? TT)02 O i[7 To] O2 g n d [T T ] cp DESCRIPTION — The ’379 is a 4-bit register with buffered common Enable.


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    /54LS/74LS379 74LS379PC 74LS379DC 74LS379FC 54LS379DM 54/74LS BA335 PDF

    SN74LS374

    Abstract: 5N54LS ls374 LS373 SN54LS374 texas instruments ls374 L537 SN54LS373 SN54S373 SN54S374
    Text: SN54LS373, SN 54LS 374, S N 54S 373, S N 54S 374, SN 74LS 373, SN 74LS374. S N 74S 373, S N 74S 374 SDLS165 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS OCTOBER 1975 —REVISED MARCH 1988 S N 5 4 L S 3 7 3 . S IM 5 4 L S 3 7 4 . S N 5 4 S 3 7 3 ,


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    SDLS165 SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374. SN74S373, SN74S374 CS373 SN74LS374 5N54LS ls374 LS373 SN54LS374 texas instruments ls374 L537 SN54LS373 SN54S373 SN54S374 PDF

    74LS373

    Abstract: SP74HCT373 SP74HCT373J SP74HCT373N
    Text: SP I SP74HCT373 ! OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS PIN CO NFIGURATION FEATURES • Designed for driving high-capacitance or low impedance loads in bus-oriented systems ■ 3-state outputs for line drivers ■ Pin compatible with 74LS373 ■ SPI CMOS technology


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    SP74HCT373 74LS373 SP74HCT373 74LS373. IPRC3CE55ES 74LS373 SP74HCT373J SP74HCT373N PDF

    74LS534

    Abstract: SN74LS534N 74LS53 74LS SN74LS534 4LS374 SN74LS374AN
    Text: Am25LS374A • Am54LS/74LS374A Am25LS534Am54LS/74LS534 8-Bit Registers with Three-State Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • 8-bit, high-speed parallel registers • Positive, edge-triggered, D-type flip-flops • Buffered common clock and buffered common three-state


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    Am25LS374A Am54LS/74LS374A Am25LS534 Am54LS/74LS534 Am25LS/54LS Am25LS Am54/74LS MIL-STD-883 74LS534 SN74LS534N 74LS53 74LS SN74LS534 4LS374 SN74LS374AN PDF

    sh54

    Abstract: No abstract text available
    Text: MOTOROLA SH54/74LS37 R nn fi ryi ryi ly i ryi -ÉdJ Li> "jjp 8" I— E>] Q U A D 2-INPUT N A N D BUFFER □ LU HI LU ili LU LU LOW ROW ER SCH O TTKY J Suffix — Case 632-08 Ceramic N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES S YM B O L


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    SH54/74LS37 sh54 PDF

    SN74LS573

    Abstract: No abstract text available
    Text: Advance Information SN54LS573/SN74LS573 OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS G EN E R A L DESCRIPTION - The 54LS/74LS573 is a High-Speed Octal Latch with Buffered Common Latch Enable LE and Buffered Common Output Enable (OE) inputs. This device is functionally identical to the 54LS/74LS373, but has different pin­


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    SN54LS573/SN74LS573 54LS/74LS573 54LS/74LS373, 54LS/74LS373 SN74LS573 PDF

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS374 OCTAL D TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS Feature • • • • • D-Type-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock/Enable Input Has Hysteresis to Improve Noise Rejection


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    GD54/74LS374 74LS374 PDF

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS377 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP FLOP WITH ENABLE Features Pin Configuration • • Eight-bit, high speed parallel registers Positive, edge-triggered, D-type flip-flops • Buffered common clock and buffered common clock enable Vcc 8Q


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    GD54/74LS377 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LS375 Signetics Latch Quad Bistable Latch Product Specification Logic Products FEATURES TYPE • Quad transparent latch • Complementary outputs T Y P IC A L PR O P A G A TIO N D E LA Y T Y P IC A L SU PP LY C U R R E N T TO T A L 1 2 ns 6.3m A 74LS375


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    74LS375 1N916, 1N3064, 500ns PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LS375, 74LS375 4 BIT BISTABLE LATCHES OCTOBER 1 9 7 6 - REVISED M AR C H 1988 SN 54LS375 . . . J OR W PACKAGE SN 74LS375 . . . D O R N PACKAGE Supply Voltage and Ground on Corner Pins To Sim p lify P-C Board La y o u t TOP VIEW ID £ ^1 6 IQ description


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    SN54LS375, SN74LS375 54LS375 74LS375 54LS375 74LS375 SN54LS75 SN74LS75, SN54LS375 SN74LS375. PDF

    DN74LS373

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series DN 74LS373 74LS373 K>74 LS. 373 Octal D-type Transparent Latches with 3 -sta te Outputs • Description D N 74L S 373 con tain s eight 3-state o u tp u t D -type latch circuits w ith com m on o u tp u t-c o n tro l enable in puts for all circuits.


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    DN74LS DN74LS373 DN74LS373 400mV 20-pin SO-20D) PDF

    74LS377PC

    Abstract: ls 377 54LS377DM 54LS377FM 74LS377DC 74LS377FC CP1020
    Text: 377 C O N N E C T IO N D IA G R A M P IN O U T A 54LS/74LS377 O C TA L D FLIP-FLO P W ith C om m on Enable and Clock D E S C R IP T IO N — T he '377 is an 8 -b it re g iste r b u ilt using advanced lo w p o w e r S c h o ttk y te c h n o lo g y . T h is reg iste r co n sists o f e ig h t D -typ e flip -flo p s w ith a


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    54LS/74LS377 20-pin 74LS377PC 74LS377DC 74LS377FC 54/74LS S4/74LS 74LS377PC ls 377 54LS377DM 54LS377FM 74LS377DC 74LS377FC CP1020 PDF

    25LS07

    Abstract: 25LS08 74ls175 p
    Text: 80S~ISZUJV/Z0S~ISZUJV Am25LS07/Am25LS08 Hex/Quad Parallel D Registers with Register Enable DISTINCTIVE CHARACTERISTICS • • • • 4-bit and 6-bit parallel registers Common Clock and Common Enable Positive edge triggered D flip flops Second sourced by Tl as 54LS/74LS378 and 379


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    Am25LS07/Am25LS08 54LS/74LS378 Am25LS 440/jA Am25LS07 Am25LS08 Am54LS/74LS174 Am54LS/ 74LS175 25LS07 25LS08 74ls175 p PDF

    SN74LS374AN

    Abstract: 74ls534 74LS53 SN74LS534N AM26LS37
    Text: Am25LS374A • Am54LS/74LS374A Am25LS534Am54LS/74LS534 8-Bit Registers with Three-State Outputs DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • 8-bit, high-speed parallel registers • Positive, edge-triggered, D-type flip-flops • Buffered common clock and buffered common three-state


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    Am25LS374A Am54LS/74LS374A Am25LS534 Am54LS/74LS534 Am25LS/54LS Am25LS Am54/74LS MIL-STD-883 SN74LS374AN 74ls534 74LS53 SN74LS534N AM26LS37 PDF

    74198

    Abstract: 74LS194 74198 pin diagram 54LS D172 D173 74LS273 74LS323 74ls273 fairchild 74LS398
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL 088 54LS/74LS299 11 18 Vcc Pin 20 QND = Pin 10 D89 54LS/74LS323 Vcc = Pin 20 QND = Pin 10 D90 54LS/74LS273 3 4 7 8 13 14 17 18 Vcc = Pin 20 GND = Pin 10 D91 54LS/74LS377 1 3 4 7 8 13 14 17 18 Vcc = Pin 20 GND = Pin 10


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    54LS/74LS299 54LS/74LS323 54LS/74LS273 54LS/74LS377 54LS/74LS378 PilliD150 54LS/74LS298 /74LS395 /74LS273 /74LS374 74198 74LS194 74198 pin diagram 54LS D172 D173 74LS273 74LS323 74ls273 fairchild 74LS398 PDF