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    74LS00 GATE DIAGRAM NAND Search Results

    74LS00 GATE DIAGRAM NAND Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    TLP5702H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TLP5705H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    GT30J110SRA Toshiba Electronic Devices & Storage Corporation IGBT, 1100 V, 60 A, Built-in Diodes, TO-3P(N) Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    74LS00 GATE DIAGRAM NAND Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    pin diagram of ic 74ls00

    Abstract: M74HCT00B1 74LS00 gate diagram M74HCT00 74LS00 IC 74LS00 M54HCT00 M54HCT00F1R 74HCT00 M74HCT00C1R
    Text: M54HCT00 M74HCT00 QUAD 2-INPUT NAND GATE . . . . . . . HIGH SPEED tPD = 12 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUTS DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS


    Original     		PDF M54HCT00 M74HCT00 54/74LS00 M54/74HCT00 pin diagram of ic 74ls00 M74HCT00B1 74LS00 gate diagram M74HCT00 74LS00 IC 74LS00 M54HCT00 M54HCT00F1R 74HCT00 M74HCT00C1R

    pin diagram of ic 74ls00

    Abstract: 74LS00 gate diagram 74LS00 circuit diagram with voltage 74LS00 CMOS M74HCT00 74LS00 M54HCT00 M54HCT00F1R 74ls00 circuit diagram M74HCT00C1R
    Text: M54HCT00 M74HCT00 QUAD 2-INPUT NAND GATE . . . . . . . HIGH SPEED tPD = 12 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUTS DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS


    Original     		PDF M54HCT00 M74HCT00 54/74LS00 M54/74HCT00 pin diagram of ic 74ls00 74LS00 gate diagram 74LS00 circuit diagram with voltage 74LS00 CMOS M74HCT00 74LS00 M54HCT00 M54HCT00F1R 74ls00 circuit diagram M74HCT00C1R

    Untitled

    Abstract: No abstract text available
    Text: SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 D Package Options Include Plastic Small-Outline D, NS, PS , Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and


    Original     		PDF SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 SDLS025B SN5400

    Untitled

    Abstract: No abstract text available
    Text: SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 D Package Options Include Plastic Small-Outline D, NS, PS , Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and


    Original     		PDF SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 SDLS025B SN5400

    Untitled

    Abstract: No abstract text available
    Text: SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 D Package Options Include Plastic Small-Outline D, NS, PS , Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and


    Original     		PDF SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 SDLS025B SN5400 SN54S00

    Untitled

    Abstract: No abstract text available
    Text: SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 D Package Options Include Plastic Small-Outline D, NS, PS , Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and


    Original     		PDF SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 SDLS025B SN5400

    internal structure 74LS00 nand gate

    Abstract: MM74HC ic mm74hc IC TTL 74LS00 CD4000 FAIRCHILD MM74HC AN-313 mm74c CMOS TTL Logic Family Specifications CD4000 NAND
    Text: Fairchild Semiconductor Application Note 313 Larry Wakeman April 1998 The input and output characteristics of the MM74HC high-speed CMOS logic family were conceived to meet several basic goals. These goals are to provide input current and voltage requirements, noise immunity and quiescent


    Original     		PDF MM74HC CD4000 MM74C MM74HCT MM74HC internal structure 74LS00 nand gate ic mm74hc IC TTL 74LS00 FAIRCHILD MM74HC AN-313 CMOS TTL Logic Family Specifications CD4000 NAND

    TEXAS INSTRUMENTS SN7400 SERIES

    Abstract: sn7400
    Text: SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SDLS025A − DECEMBER 1983 − REVISED AUGUST 2003 D Package Options Include Plastic Small-Outline D, NS , Shrink Small-Outline (DB), and Ceramic Flat (W) Packages,


    Original     		PDF SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 SDLS025A SN5400 SN54S00 TEXAS INSTRUMENTS SN7400 SERIES sn7400

    ic mm74hc

    Abstract: MM74HC 74HC inverter tri-state output ic cd4000 CMOS TTL Logic Family Specifications AL 5052 CD4000 74LS SERIES cmos logic data Difference between LS, HC, HCT devices unbuffered cmos logic application note
    Text: National Semiconductor Application Note 313 Larry Wakeman June 1983 The input and output characteristics of the MM54HC MM74HC high-speed CMOS logic family were conceived to meet several basic goals These goals are to provide input current and voltage requirements noise immunity and quiescent power dissipation similar to CD4000 and MM54C


    Original     		PDF MM54HC MM74HC CD4000 MM54C MM74C MM54HCT MM74HCT MM54HC MM74HC ic mm74hc 74HC inverter tri-state output ic cd4000 CMOS TTL Logic Family Specifications AL 5052 74LS SERIES cmos logic data Difference between LS, HC, HCT devices unbuffered cmos logic application note

    CI 74LS00

    Abstract: Automatic Load Sharing between Two or More Transf CI 74LS148
    Text: ViewDraw User’s Guide Spring 2000 Copyright Page Copyright 1985, 1996, 1997, 1998, 1999, 2000 Innoveda, Inc. 293 Boston Post Road West Marlboro, Massachusetts 01752–4615 All Rights Reserved. This information is copyrighted; all rights are reserved by Innoveda, Inc. This information may


    Original     		PDF

    scba004

    Abstract: SN74LS00 74LS00 SN74LS00P SN5400 SN54LS00 SN54S00 SN7400 SN7400N SN74LS00N
    Text: SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 D Package Options Include Plastic Small-Outline D, NS, PS , Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and


    Original     		PDF SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 SDLS025B SN5400 scba004 SN74LS00 74LS00 SN74LS00P SN5400 SN54LS00 SN54S00 SN7400 SN7400N SN74LS00N

    74LS00 CMOS

    Abstract: 74LS00 gate diagram 74LS00 circuit diagram with voltage ttl 74ls00 series 74LS00 pinout CMOS 74LS00 74LS00 gate diagram nand 74LS00 74LS00 QUAD 2-INPUT NAND GATE pin diagram of 74ls00
    Text: S AN YO SEMICONDUCTOR CORP 1EE. D I 7 cn 7 0 7 b QODBS^ T -m -zi ¡•HlBl C M O S High-Speed Standard Logic LC74HC Series 3034 A , Quad 2-Input NAND Gate 21 3 8A • Features • The L C 7 4 H C 0 0 M consists o f 4 identical 2-input N A N D gates. • Uses C M O S silicon gate process technology to achieve operating speeds sim ilar to L S -T T L (74LS00 w ith the


    OCR Scan     		PDF 7cH707ki LC74HC00WB LC74HC LC74HC00M 74LS00) 54LS/74LS Tas85Â 10sec LC74HC00M) 74LS00 CMOS 74LS00 gate diagram 74LS00 circuit diagram with voltage ttl 74ls00 series 74LS00 pinout CMOS 74LS00 74LS00 gate diagram nand 74LS00 74LS00 QUAD 2-INPUT NAND GATE pin diagram of 74ls00

    IC 74LS00

    Abstract: 74LS00 gate diagram 74LS00 74LS00W
    Text: S ANYO SEMICONDUCTOR CORP 1EE. D I 7 cn 7 0 7 b QODBS^ T-Hi.-2-l ¡• H lB l ’ C M O S High-Speed Standard Logic LC74HC Series 3034 A , Quad 2-Input NAND Gate 21 3 8A • Features • The L C 7 4 H C 0 0 M consists o f 4 identical 2-input N A N D gates.


    OCR Scan     		PDF n707b LC74HC 74LS00) 10sec 5306KI/4106KI IC 74LS00 74LS00 gate diagram 74LS00 74LS00W

    74LS00 integrated circuit

    Abstract: No abstract text available
    Text: r z 7 S C S TH O M S O N Ä 7# M54HCT00 M74HCT00 QUAD 2-INPUT NAND GATE • HIGH SPEED tpD = 12 ns 7YP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 HA (MAX.) AT Ta = 25 ”C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) V il = 0.8V (MAX) ■ OUTPUTS DRIVE CAPABILITY


    OCR Scan     		PDF M54HCT00 M74HCT00 54/74LS00 M54/74HCT00 74LS00 integrated circuit

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­


    OCR Scan     		PDF GD54/74HC00, GD54/74HCT00 54/74LS00.

    TTL 74HC00

    Abstract: 74LS00 TTL TTL 74ls00 74LS00 gate diagram 74ls00 74LS00 function table pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00
    Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­


    OCR Scan     		PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 D0Q457Q TTL 74HC00 74LS00 TTL TTL 74ls00 74LS00 gate diagram 74ls00 74LS00 function table pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00

    IC 74LS00

    Abstract: 74LS00 gate diagram nand IC TTL 74LS00 M74HCT00
    Text: S G S -T H O M S O N jL iM s iO (g S M 5 4 H C T oo M74HCT00 QUAD 2-INPUT NAND GATE • H IG H S P E E D tp D = 12 ns (TYP.) AT V c c = 5 V ■ LO W PO W ER DISSIPATION Ice = 1 |iA (M AX.) A T T a = 2 5 °C ■ C O M P A TIB LE W ITH TTL O U TP U TS V ih = 2V (MIN.) V il = 0.8V (MAX)


    OCR Scan     		PDF M74HCT00 54/74LS00 54/74HCT00 IC 74LS00 74LS00 gate diagram nand IC TTL 74LS00

    Untitled

    Abstract: No abstract text available
    Text: M IT S U B IS H I HIGH SPEED CMOS M 7 4 H C P M 7 4 H C D P QUADRUPLE 2 -IN P U T P O S IT IV E NAND GATE DESCRIPTION PIN The M 74H C 00 is a sem iconductor inte grated c ircu it con­ CONFIGURATION TOP VIEW sisting of fou r 2-in put p o s itiv e -lo g ic NAND, usable as negativ e -lo g ic NOR gates.


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    IC TTL 74LS00

    Abstract: 74ls00 74LS00 gate diagram
    Text: MITSUBISHI HIGH SPEED CMOS M74HCT00P/FP/DP QUADRUPLE 2-INPUT POSITIVE NAND GATE WITH L S TTL-C O M P A TIB LE INPUTS DESCRIPTION The M74HCT00P is a semiconductor integrated circuit con­ sisting of four 2-input positive-logic NAND gates, usable as negative-logic NOR gates.


    OCR Scan     		PDF M74HCT00P/FP/DP M74HCT00P 74LSTTL G--06 IC TTL 74LS00 74ls00 74LS00 gate diagram

    pin diagram of ic 74ls00

    Abstract: M74HC00 74LS00 transfer function 74LS00 gate diagram pin diagram of 74ls00 M74HC00P 74LS00 pin configuration 74ls00 circuit diagram M74HCOO IC PIN CONFIGURATION OF 74LS00
    Text: M IT S U B IS H I HIGH S P E E D C M O S M 74HC00P M 74HC00DP Q U A D R U P L E 2 -IN P U T P O S IT IV E N A N D G A T E DESCRIPTION T he M 74H C 00 ts a sem iconductor integrated circuit con­ sisting of fou r 2-input p o sitive-lo gic NAND, usable as nega­


    OCR Scan     		PDF M74HC00P M74HC00DP M74HC00 pin diagram of ic 74ls00 74LS00 transfer function 74LS00 gate diagram pin diagram of 74ls00 74LS00 pin configuration 74ls00 circuit diagram M74HCOO IC PIN CONFIGURATION OF 74LS00

    M74HCOO

    Abstract: M74HC00D
    Text: M IT S U B IS H I HIGH SPEED CMOS M 74H C 00 P /F P /D P QU A D RU PLE 2 -IN P U T P O S IT IV E NAND GATE DESCRIPTION The M 7 4 H C 0 0 is a s e m ic o n d u c to r in te g r a te d c irc u it c o n ­ sis tin g of fo u r 2 -in p u t p o s itiv e -lo g ic N A N D g a te s , u s a b le as


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    IC AND GATE 7408 specification sheet

    Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
    Text: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format


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    SN74H00

    Abstract: SN54H00S
    Text: TYPES SN5400, SN54H00, SN54L00, SN54LS00, SN54S00, SN7400, SN74H00, SN74LS00, SN74S00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES _ • Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs _ R E V IS E D D E C E M B E R 1 9 8 3


    OCR Scan     		PDF SN5400, SN54H00, SN54L00, SN54LS00, SN54S00, SN7400, SN74H00, SN74LS00, SN74S00 SN54LOO SN74H00 SN54H00S

    74LS205

    Abstract: No abstract text available
    Text: / 'K -v 1 DESCRIPTION The MN5500 is a 12 Bit A/D Converter designed specifically for microprocessor applications. Internal circuitry is sup­ plied for chip select, address decoding, and the other inter­ face signals required by popular microprocessors. In most


    OCR Scan     		PDF MN5500 conver02 MN2020 74LS175 74LS00 74LS02 74LS04 74LS20 74LS205