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    74LS* FAN IN Search Results

    74LS* FAN IN Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    PQU650M-F-COVER Murata Manufacturing Co Ltd PQU650M Series - 3x5 Fan Cover Kit, RoHs Medical Visit Murata Manufacturing Co Ltd
    74LS491ANS Rochester Electronics LLC Replacement for AMD part number SN74LS491ANS. Buy from authorized manufacturer Rochester Electronics. Visit Rochester Electronics LLC Buy
    74LS626N Rochester Electronics LLC Replacement for Texas Instruments part number SN74LS626N. Buy from authorized manufacturer Rochester Electronics. Visit Rochester Electronics LLC Buy
    74LS190N Rochester Electronics LLC Replacement for Texas Instruments part number SN74LS190N. Buy from authorized manufacturer Rochester Electronics. Visit Rochester Electronics LLC Buy
    74LS468N Rochester Electronics LLC Replacement for Texas Instruments part number SN74LS468N. Buy from authorized manufacturer Rochester Electronics. Visit Rochester Electronics LLC Buy

    74LS* FAN IN Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CD4014BM CD4014BC 8-Stage Static Shift Register General Description Dual-In-Line Package Features Y Y Y Y Y Y Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VDD typ Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS 5V – 10V – 15V parametric ratings


    Original     		PDF CD4014BM CD4014BC

    74LS

    Abstract: CD4015BC CD4015BM 18VQC
    Text: CD4015BM/CD4015BC i/W \ National m!m Semiconductor CD4015BM/CD4015BC DUAL 4-BIT Static Shift Register General Description fan ou t o f 2 d rivin g 74L or 1 driving 74LS Low pow er TTL c o m p a tib ility The CD4015BM/CD4015BC c o n ta in s tw o id e n tic a l,


    OCR Scan     		PDF CD4015BM/CD4015BC 74LS CD4015BC CD4015BM 18VQC

    Untitled

    Abstract: No abstract text available
    Text: October 1987 Revised January 1999 S E M ¡ C O N D U C T O R TM Features • Wide supply voltage range: ■ High noise immunity: 3.0V to 15V 0.45 Vqq typ. ■ Low power TTL compatibility: or 1 driving 74LS ■ New formula: C in Farads) PW 0 ut = RC Fan out of 2 driving 74L


    OCR Scan     		PDF CD4528BC CD4538BCM 16-Lead CD4538BC

    54LS365ADM

    Abstract: 54LS365AFM 74LS365ADC 74LS365AFC 74LS365APC 74LS365AD
    Text: 365A CONNECTIO N DIAGRAM PINOUT A J 54LS /74LS 365A HEX 3-STATE BUFFER W ith C om m on 2 -In p u t NOR Enable ORDERING CODE: See Section 9 PIN PKGS Plastic DIP <P) Ceramic DIP <D) Flatpak (F ) OUT COM M ERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%, = 0° C t o +70° C


    OCR Scan     		PDF 54LS/74LS365A 74LS365APC 74LS365ADC 74LS365AFC 54LS365ADM 54LS365AFM 54/74LS 54/74LS 54LS365ADM 54LS365AFM 74LS365ADC 74LS365AFC 74LS365APC 74LS365AD

    74LS20PC

    Abstract: 74LS20 74LS20P pinout 7420 7420PC
    Text: 20 CO NNECTIO N DIAGRAMS PINOUT A '54/7420 öf 2 ^ / 54H/74H20 S ' O P ' l l/54S/74S20 0 / 0 / 3 1 ^¿4LS /74LS 20 ¿ ? / r / 3 * DUAL 4-INPUT NAND GATE ORDERING CODE: See Section 9 CO M M ERCIAL GRADE PIN PKGS OUT MILITARY GRADE Vcc = +5.0 V ±5%, Vcc = +5.0 V ±10%,


    OCR Scan     		PDF 54H/74H20 l/54S/74S20 /74LS 7420PC, 74H20PC 74S20PC, 74LS20PC 7420DC, 74H20DC 74S20DC, 74LS20 74LS20P pinout 7420 7420PC

    Untitled

    Abstract: No abstract text available
    Text: 133 CO NNECTIO N DIAGRAM PINOUT A J 54S/74S133 O / ô ^ 54LS/74LS133 o / ¿vsW 13-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS O UT CO M M ERCIAL GRADE M ILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C V cc = +5.0 V ±10%, T a = -55° C to +125°C


    OCR Scan     		PDF 54S/74S133 54LS/74LS133 13-INPUT 74S133PC, 74LS133PC 74S133DC, 74LS133DC 74S133FC, 74LS133FC 54S133DM,

    74LS00P

    Abstract: 74LS00 pinout 74LS00 fan-out 74LS00 7400 74S00 7400 fan-out 74LS00PC 7400PC 74LS00 74LS00D 74LS00DC
    Text: 00 CO NNECTIO N DIAGRAMS PINOUT A 54/7400 ^ o n et* 54H /74H 00Ä eU9 5 4 S /7 4 S 0 0 ^' /V 54LS/74LS00^'/ bUi QUAD 2-INPUT NAND GATE ORDERING CODE: See Section 9 CO M M ERCIAL GRADE PIN PKGS Vcc = +5.0 V ±5%, = 0° C to +70° C OUT M ILITARY GRADE Vcc = +5.0 V ±10%,


    OCR Scan     		PDF 54H/74H00 54S/74S00 54LS/74LS00^ 54/74H 54/74S 54/74LS 7400PC, 74H00PC 74LS00PC, 74S00PC 74LS00P 74LS00 pinout 74LS00 fan-out 74LS00 7400 74S00 7400 fan-out 74LS00PC 7400PC 74LS00 74LS00D 74LS00DC

    NAND Gate 3-Input 7410

    Abstract: 74LS10PC
    Text: 10 CO NNECTIO N DIAGRAMS PINO UT A '''54/7410 ^é4H/74H10 ^54S/74S10 ö / ' o -h? ^ 4 L S /7 4 L S 1 0 ^ / y 7 TRIPLE 3-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE M ILITARY GRADE V cc = +5.0 V ±5%, T a = 0° C to +70° C


    OCR Scan     		PDF 4H/74H10 54S/74S10 7410PC, 74H10PC 74S10PC, 74LS10PC 7410DC, 74H10DC 74S10DC, 74LS10DC NAND Gate 3-Input 7410

    rs flip-flop IC 7400

    Abstract: 74ls105 TTL LS 7400 74LS series logic gates 7400 fan-out 74LS 3 input AND gate IC TTL 7400 schematic 74LS04 fan-out 74ls series logic family 90 watts inverter by 12v dc with 6 transisters
    Text: GENERAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS Ovar operating free-air temper­ ature range unless otherwise noted Supply Voltage Vq c (See Note 1) Input Voltage V|n (See Note 1) Interemitter Voltage (See Note 2) Resistor Node Voltage, 54121, 74121 (See Note 1)


    OCR Scan     		PDF

    IC 7422

    Abstract: IC 7422 g 74H22
    Text: 22 CO NNECTIO N DIAGRAMS PINOUT A 54/7422 6 / ' ô < / 54H/74H22 > w/ o4S/74S22 o / ¿ 5 v54LS/74LS22 ,v/j> <r DUAL 4-INPUT NAND GATE With O pen-Collector Output ORDERING CODE: See Section 9 COMM ERCIAL GRADE PIN PKGS Vcc = +5.0 V ±5%, = 0 °C to +70° C


    OCR Scan     		PDF 54H/74H22 o4S/74S22 v54LS/74LS22 7422PC, 74H22PC 74S22PC, 74LS22PC 7422DC, 74H22DC 74S22DC, IC 7422 IC 7422 g 74H22

    7451 ic

    Abstract: 54S51 74LS51 74H51PC
    Text: 51 CO NNECTIO N DIAGRAMS PINOUT A Offo-pfa 1/^4/7451 v^4H /74H 51 r -h M i S4S/74S51 ' - ’ ^Ö4LS/74LS51 m h ò ' f DUAL 2-WIDE, 2-INPUT AOI GATE DUAL 2-WIDE, 2-INPUT/3-INPUT AOI GATE CLS51 ORDERING CODE: See Section 9 PIN PKGS Plastic DIP P) Ceramic DIP (D)


    OCR Scan     		PDF S4S/74S51 4LS/74LS51 CLS51) 74H51PC 74S51PC 74LS51PC 74H51DC 74S51DC 74LS51DC 74S51FC 7451 ic 54S51 74LS51

    74LS30PC

    Abstract: 74LS30 74LS30P 7430DC
    Text: 30 CO NNECTIO N DIAGRAMS PINO UT A 54/7430 o/ô //7 54H/74H30 ò /q /s o W54S/74S30/ , \/54LS/74LS30 O Vcc d 8-INPUT NAND GATE E E E m Œ ]Ö ]N C [7 I] 1 3 ]n C 13 U gnd ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%,


    OCR Scan     		PDF 54H/74H30 W54S/74S30/ \/54LS/74LS30 7430PC, 74H30PC 74S30PC, 74LS30PC 7430DC, 74H30DC 74S30DC, 74LS30 74LS30P 7430DC

    7411 3 INPUT AND gate

    Abstract: 74LS11 dm 7411 3 input and gate 7411 74LS11 pinout 7411 and gate 74S11PC 54H11 54S11DM 74H11DC
    Text: 11 CO NNECTIO N DIAGRAMS PINOUT A ^ 4 /7 4 1 1 o/fc:- £ L 54H/74H11 3 ^ u54S/74S11 o / / 6 5 3 -54LS/74LS11 TRIPLE 3-INPUT AND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5.0 V ±10%,


    OCR Scan     		PDF 54H/74H11 u54S/74S11 -54LS/74LS11 74H11PC 74S11PC, 74LS11 74H11DC 74S11 54H11 7411 3 INPUT AND gate dm 7411 3 input and gate 7411 74LS11 pinout 7411 and gate 74S11PC 54S11DM

    74ls786

    Abstract: 74LS78 ic 74ls78
    Text: 78 CO NNECTIO N DIAGRAMS PINOUT A ^ 4 H /7 4 H 7 8 £ V / - 5 Ö v/54LS/74LS78 6 1> c ~ / C5 DUAL JK FLIP-FLOP With Common Clear and Clock and Separate Set Inputs DESCRIPTION — The 'H78 is a dual JK master/slave flip -flo p with separate Direct Set inputs, a common Direct Clear input and a common C lock Pulse


    OCR Scan     		PDF v/54LS/74LS78 54/74H 54/74LS CLS78) 74ls786 74LS78 ic 74ls78

    Untitled

    Abstract: No abstract text available
    Text: 256 CO NN ECTIO N DIAGRAM PINOUT A 54LS/74LS256 v n u ~ f DUAL 4-BIT ADDRESSABLE LATCH AoQ SI VCC A ,H i s ] CL 14J È D „ [3 Qoa ^ DESCRIPTION — The ’256 is a dual 4-b it addressable latch w ith com m on control inputs; these include tw o Address inputs Ao, Ai , an active LOW En­


    OCR Scan     		PDF 54LS/74LS256 54/74LS

    74LS40

    Abstract: 74LS40D IC 7440
    Text: 40 CO NNECTIO N DIAGRAMS PINOUT A 54/7440 0 '° / l^ H / 7 4 H 4 0 o n o ^ 'v ^ 4 S / 7 4 S4 0 o / f c L/'l ^54LS/74LS40 C'Oi DUAL 4-INPUT NAND BUFFER ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE M ILITARY GRADE Vcc = +5.0 V ±5%, T a = 0 °C to +70° C


    OCR Scan     		PDF 54LS/74LS40 7440PC, 74H40PC 74S40PC, 74LS40PC 7440DC, 74H40DC 74S40DC, 74LS40DC 74S40FC, 74LS40 74LS40D IC 7440

    5437DM

    Abstract: No abstract text available
    Text: 37 CO NNECTIO N DIAGRAM PINOUT A .54/7437 ¿' 'S 7b. 54LS/74LS37 0 / / j 77 QUAD 2-INPUT NAND BUFFER OROERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, Ta = 0°C to +70° C V cc = +5.0 V ±10%, T a = -55° c to +125°C


    OCR Scan     		PDF 54LS/74LS37 7437PC, 74LS37PC 7437DC, 74LS37DC 7437FC, 74LS37FC 5437DM, 54LS37DM 5437FM, 5437DM

    7438PC

    Abstract: 74LS38PC 5438DM 74LS38 5438FM 54LS38DM 54LS38FM 7438DC 7438FC 74LS38DC
    Text: 38 CONNECTIO N DIAGRAM P IN O U T A ¡4/7438 V^4/ 6 / / -b 2 ^ l/5 4 L S /7 4 L S 3 8 ous ?‘r/ QUAD 2-IN PU T NAND BUFFER With O pen-Collector Output ORDERING CODE: See S e ctio n 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE V cc = + 5.0 V ±5%, V cc = + 5.0 V ±10% ,


    OCR Scan     		PDF l/54LS/74LS38^ 7438PC, 74LS38PC 7438DC, 74LS38DC 5438DM, 54LS38DM 7438FC, 74LS38FC 5438FM, 7438PC 74LS38PC 5438DM 74LS38 5438FM 54LS38FM 7438DC 7438FC

    F7474PC

    Abstract: 74ls74d 7474 pin out diagram ic 7474 pin diagram 74H74D 7474PC IC 74LS74 pin IC 7474 74LS74PC IC 7474 flipflop
    Text: 74 C O N N E C T IO N DIAGRAM S P IN O U T A 54/7474 < ? / / 6 ' \/54H/74H74 t f e. j w w^4S/74S74 £>/, o 'b, U34LS/74LS74 ^ ^ < - 3 ^ — "Si / / DUAL D-TYPE POSITIVE ED G e"TRIGGERED FLIP-FLOP P IN O U T B DESCRIPTIO N — The ’74 devices are dual D-type flip-flops with Direct C le a r


    OCR Scan     		PDF \/54H/74H74 4S/74S74 34LS/74LS74 54/74H 54/74S 54/74LS F7474PC 74ls74d 7474 pin out diagram ic 7474 pin diagram 74H74D 7474PC IC 74LS74 pin IC 7474 74LS74PC IC 7474 flipflop

    74ls189 ram

    Abstract: 74LS189 74LS189 logic diagram 74LS189DC 74LS189PC 74LS189FC 74S189DC 54LS189DM 54S189DM 74S189FC
    Text: 189 CONNECTION DIAGRAM PINOUT A ¡4S/74S189 ►54LS/74LS189 b n 7 S 0 ao [T ï i ] Vcc 64-BIT RANDOM ACCESS MEMORY C sU m a. With 3-State Outputs we |T T7| A2 Di [7 Ö1 [ ? j l ] A3 02 ï D ESC R IPTIO N — The '189 is a high speed 64-bit RAM organized as a 16word by 4 -b it array. Address inputs are buttered to m inimize loading and are


    OCR Scan     		PDF 4S/74S189 54LS/74LS189 64-BIT 16-word CLS189) 54/74S 54/74LS 74ls189 ram 74LS189 74LS189 logic diagram 74LS189DC 74LS189PC 74LS189FC 74S189DC 54LS189DM 54S189DM 74S189FC

    Untitled

    Abstract: No abstract text available
    Text: 49 CO NNECTIO N DIAGRAM PINOUT A 5 4 /7 4 4 9 ' 54LS/74LS49* I BCD TO 7-SEGMENT DECODER I vcc Ai [T tu Aa Q [ 7 ä ]f BÎ [ T U b TT] a Ao [ T To] b •E 3« GND [ 7 jQd DESCRIPTION — The '49 translates fou r lines o f BCD 8421 input data into the 7-segment numeral code as shown in the Truth Table. It has open-collector outputs and is logically the 14-pin version of the '48, w ithout the lamp


    OCR Scan     		PDF 54LS/74LS49* 14-pin LS249 74LS49PC 74LS49DC 7449FC, 74LS49FC 54LS49DM 5449FM, 54LS49FM

    74LS83AP

    Abstract: 7483AP 7483APC 74LS83APC 54LS83ADM 74LS83ADC 7483 5483ADM 5483AFM 54LS83AFM
    Text: 83A CONNECTION DIAGRAM PINOUT A o / &I ^ ’ ‘ 54LS/74LS83A Ï 4-BIT BINARY FULL ADDER W ith Fast Carry / a3|T Të] S3 s2(T Ts] s3 a 2[7 Î4|C< b2 T3] Co [7 12] GND vcc [ I Si T I bo [7 TÖ1 Ao Ai [S "9] So B, DESCRIPTION — The ’83A high speed 4-bit binary fu ll adders w ith internal


    OCR Scan     		PDF pOl4/74Q3A 54LS/74LS83A 7483APC, 74LS83APC CLS83A) 54/74LS 74LS83AP 7483AP 7483APC 74LS83APC 54LS83ADM 74LS83ADC 7483 5483ADM 5483AFM 54LS83AFM

    Difference between LS, HC, HCT devices

    Abstract: TC4S69F Small Signal Zener Diod difference between 74ls and 74hc ic TC74HC04
    Text: C2MOS Logic TC74HC/HCT Series 9. Precautions in Designing Circuits 9-1 Input Processing 1 Processing of unused gate Inputs of CMOS IC have such a high impedance that the logic level becomes undefined under open conditions. If the input is at an intermediate level, the P-channel and Nchannel transistors both turn on, and excessive supply


    OCR Scan     		PDF TC74HC/HCT TC74HC08 TC7S32F TC74HC32 TC7S02F TC7SU04F TC74HCU04 TC7S00F TC7S04F TC74HC00 Difference between LS, HC, HCT devices TC4S69F Small Signal Zener Diod difference between 74ls and 74hc ic TC74HC04

    16 bit comparator 74ls

    Abstract: 8bit counter 74ls successive approximation 54LS502DM 54LS502FM 74LS502FC 74LS502PC 74LS502
    Text: 502 CO NNECTIO N DIAGRAM PINOUT A {(Q^ 54LS /74LS 502 8-B IT SUCCESSIVE APPR O XIM ATIO N REGISTER DESCRIPTION — The ’LS502 is an 8-bit register w ith the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Com plete (CC signal coincident with storage of the eighth


    OCR Scan     		PDF 54LS/74LS502 LS502 16 bit comparator 74ls 8bit counter 74ls successive approximation 54LS502DM 54LS502FM 74LS502FC 74LS502PC 74LS502