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    Untitled

    Abstract: No abstract text available
    Text: M I T S U B I S H I -CDGTL L O GI C} =11 6 2 4 9 8 2 7 M I T S U B I S H I D G T L L O G I C Q >/ 9 1D 12 182 De J bEMTÖS? GOlSlflS 1 MITSUBISHI ASTTLs M 74AS20P T 'V 3 DUAL 4 -INPUT POSITIVE NAND GATE DESCRIPTION Th e PIN CONFIGURATION (TOP VIEW) M 7 4A S 2 0P is a sem iconductor integrated circuit


    OCR Scan     		PDF 74AS20P 24P4D 24-PIN

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI ASTTLs pS?< 74AS20P DUAL 4 -INPUT POSITIVE NAND G ATE DESCRIPTION PIN CONFIGURATION TOP VIEW The 74AS20P is a semiconductor integrated circuit consisting of two 4-input positive-logic NAND gates, us­ able as negative-logic NOR gates. FEATURES


    OCR Scan     		PDF M74AS20P M74AS20P