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    74AC11 Search Results

    74AC11 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74AC11828NT Rochester Electronics LLC Bus Driver, Visit Rochester Electronics LLC Buy
    74AC11158N Rochester Electronics LLC Multiplexer, Visit Rochester Electronics LLC Buy
    74AC11191DW Rochester Electronics LLC Binary Counter, Visit Rochester Electronics LLC Buy
    74AC11086D Texas Instruments Quadruple 2-Input Exclusive-OR Gates 16-SOIC -40 to 85 Visit Texas Instruments Buy
    74AC11244DW Texas Instruments Octal Buffers/Drivers 24-SOIC -40 to 85 Visit Texas Instruments Buy
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    74AC11 Price and Stock

    Texas Instruments SN74AC11DR

    IC GATE AND 3CH 3-INP 14SOIC
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    DigiKey SN74AC11DR Cut Tape 5,118 1
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    Bristol Electronics SN74AC11DR 2,411
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    Rochester Electronics SN74AC11DR 1,475 1
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    Ameya Holding Limited SN74AC11DR 120,862
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    ComSIT USA SN74AC11DR 188
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    Chip One Stop SN74AC11DR Cut Tape 2,431
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    onsemi MC74AC11DR2G

    IC GATE AND 3CH 3-INP 14SOIC
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    DigiKey MC74AC11DR2G Digi-Reel 2,891 1
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    MC74AC11DR2G Cut Tape 2,891 1
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    MC74AC11DR2G Reel 2,500 2,500
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    Avnet Americas MC74AC11DR2G Reel 2,500 12 Weeks 2,500
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    Newark MC74AC11DR2G Cut Tape 2,409 1
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    MC74AC11DR2G Reel 2,500
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    TME MC74AC11DR2G 1
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    Avnet Silica MC74AC11DR2G 13 Weeks 2,500
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    Chip One Stop MC74AC11DR2G Cut Tape 1,875
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    EBV Elektronik MC74AC11DR2G 14 Weeks 2,500
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    Texas Instruments 74AC11240PW

    IC BUFF INVERT 5.5V 24TSSOP
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    DigiKey 74AC11240PW Tube 1,165 1
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    Texas Instruments CD74AC112M96

    IC FF JK TYPE DUAL 1BIT 16SOIC
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    DigiKey CD74AC112M96 Cut Tape 1,001 1
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    CD74AC112M96 Digi-Reel 1,001 1
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    ComSIT USA CD74AC112M96 1,122
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    Texas Instruments 74AC11032N

    IC GATE OR 4CH 2-INP 16DIP
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    DigiKey 74AC11032N Tube 532 1
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    Chip 1 Exchange 74AC11032N 304
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    Find more 74AC11 price and stock on Findchips.com

    74AC11 Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74AC11 Fairchild Semiconductor Triple 3-Input AND Gate Original PDF
    74AC11 STMicroelectronics Triple 3-Input AND Gate Original PDF
    74AC11000 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATE Original PDF
    74AC11000 Texas Instruments Quadruple 2-Input Positive-NAND Gates Original PDF
    74AC11000 Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATE Original PDF
    74AC11000D Texas Instruments Quadruple 2-Input Positive-NAND Gate Original PDF
    74AC11000D Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATE Original PDF
    74AC11000D Texas Instruments Quadruple 2-Input Positive-NAND Gates 16-SOIC -40 to 85 Original PDF
    74AC11000D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74AC11000D Texas Instruments Quad 2-input NAND Gate Scan PDF
    74AC11000D Texas Instruments QUADRUPLE 2-INPUT POSITIVE-NAND GATES Scan PDF
    74AC11000DE4 Texas Instruments Quadruple 2-Input Positive-NAND Gates Original PDF
    74AC11000DE4 Texas Instruments Quadruple 2-Input Positive-NAND Gates 16-SOIC -40 to 85 Original PDF
    74AC11000DG4 Texas Instruments Quadruple 2-Input Positive-NAND Gates 16-SOIC -40 to 85 Original PDF
    74AC11000DR Texas Instruments Quadruple 2-Input Positive-NAND Gates Original PDF
    74AC11000DR Texas Instruments Quadruple 2-Input Positive-NAND Gates 16-SOIC -40 to 85 Original PDF
    74AC11000DRE4 Texas Instruments Quadruple 2-Input Positive-NAND Gates Original PDF
    74AC11000DRE4 Texas Instruments Quadruple 2-Input Positive-NAND Gates 16-SOIC -40 to 85 Original PDF
    74AC11000DRG4 Texas Instruments Quadruple 2-Input Positive-NAND Gates 16-SOIC -40 to 85 Original PDF
    74AC11000N Texas Instruments Quadruple 2-Input Positive-NAND Gate Original PDF
    ...

    74AC11 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW


    OCR Scan     		54AC11109, 74AC11109 TI0066-- D2957, 500-mA STD-883C 300-mil 54AC11109 74AC11109 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to


    OCR Scan     		54AC11032, 74AC11032 TI0060-- D2957, 500-mA 300-mil 54AC11032 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations


    OCR Scan     		54AC11021 74AC11021 D2957. 500-mA 300-mll PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise


    OCR Scan     		54AC11002, 74AC11002 D2957, 500-mA 300-mil 54AC11002 PDF

    74AC11827

    Abstract: No abstract text available
    Text: 54AC11827, 74AC11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0155— 0 3 3 7 9 . NOVEMBER 1989— REVISED MARCH 1990 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers 54AC11827 . . . JT PACKAGE 74AC11827 . . . DW OR NT PACKAGE TOP VIEW


    OCR Scan     		54AC11827, 74AC11827 10-BIT TI0155-- 500-mA 300-mll PDF

    D2957

    Abstract: No abstract text available
    Text: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations


    OCR Scan     		500-mA 300-mll AC11240 AC11244, D2957 PDF

    D3318

    Abstract: No abstract text available
    Text: 74AC11139 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER D3318, JULY 1989 - R EV ISED APRIL 1993 * Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems * Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception


    OCR Scan     		74AC11139 D3318, 500-mA 300-mil 4AC11139 D3318. D3318 PDF

    74AC11520

    Abstract: No abstract text available
    Text: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations


    OCR Scan     		54AC11520 74AC11520 D2957, 500-mA 300-mil 54AC11520 74AC11S20. PDF

    2a117

    Abstract: No abstract text available
    Text: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to


    OCR Scan     		54AC11158, 74AC11158 TI010 500-mA 300-mil 54AC11158 74AC11158 2a117 PDF

    D3348

    Abstract: 74AC11151
    Text: 74AC11151 1-0F-8 DATA SELECTOR/MULTIPLEXER D3348, JUNE 1989 - REVISED APRIL 1993 * 8-Llne to 1-Llne Multiplexers Can Perform as Boolean Function Generators, Parallel-to-Serlal Converters, or Data Source Selectors * Flow-Through Architecture Optimizes PCB Layout


    OCR Scan     		74AC11151 D3348, 500-mA 300-mil D3348 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to


    OCR Scan     		74AC11004 TI0044-- D2957, 500-mA 300-mil 54AC11004 74AC11004 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74AC11204 HEX INVERTER/CLOCK DRIVER D3427, O C TO B ER 1989 DW OR N PACKAGE Low-Skew Propagation Delay Specifications for Clock Driver Applications TOP VIEW 1Y[ 1 2Y [ 2 3Y [ 3 Flow-Through Architecture Optimizes PCB Layout * * * Package Options Include Plastic “Small


    OCR Scan     		74AC11204 D3427, 500-mA 300-mil PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11853, 74AC 11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS TI0157— D3473, MARCH 1990 54AC11B53 . . . JT PACKAGE 74AC11853 . . . DW OR NT PACKAGE High-Speed Bus Transceivers with Parity Generator/Checker TOP VIEW Parity Error Flag Open-Drain Output • Register for Storage of the Parity Error Flag


    OCR Scan     		54AC11853, TI0157-- D3473, 500-mA 300-mil 54AC11B53 74AC11853 54AC11853 74AC11853 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [


    OCR Scan     		54AC11377, 74AC11377 TI0180-- D3420, 500-mA 300-mll 54AC11377 PDF

    74AC11873

    Abstract: No abstract text available
    Text: 54AC11873, 74AC11873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS • 54A C 11 8 73 . . . J T P A C K A G E 3-State Buffer-Type Outputs Drive Bus 74AC 11B73 . . . D W OR N T P A C K A G E Lines Directly TOP V IE W • Bus-Structured Pinout • Flow -Through A rchitecture O ptim izes PCB


    OCR Scan     		54AC11873, 74AC11873 11B73 500-m D3390, PDF

    74AC11533

    Abstract: 123D20
    Text: *»4AP11*511 744011*511 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0085— D2957, JULY 1987— REVISED JAN U AR Y 1990 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE • 8-Latches in a Single Package • 3-State Bus-Driving Inverting Outputs


    OCR Scan     		4AP11 TI0085-- D2957, 500-mA 300-mil 54AC11533 74AC11533 74AC11533 123D20 PDF

    042b

    Abstract: No abstract text available
    Text: 74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS042B - MAY 1988 - REVISED A P R IL I 996 D, N, OR PW PACKAGE TOP VIEW Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Y1 [ 1 Y2 [ 2 Incorporates Three Enable Inputs to


    OCR Scan     		74AC11138 SCAS042B 500-mA 300-mil 32-Bit 042b PDF

    TI009

    Abstract: No abstract text available
    Text: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to


    OCR Scan     		54AC11643, I0095-- D2957, 500-mA 300-mil 54AC11643 74AC11643 TI009 PDF

    74AC108

    Abstract: so 54 t 74AC11066
    Text: 54AC11086, 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0152— D3375, N O VEM BER 1989 • Flow-Through Architecture to Optimize PCB Layout 54AC11086 . . . J PACKAGE 74AC11086 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to


    OCR Scan     		54AC11086, 74AC11086 TI0152-- D3375, 500-mA 300-mil 74AC108 so 54 t 74AC11066 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11074,74AC11074 DUAL D-TYPE POSUIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, D E C E M B E R 1986 - REVISED A P R IL 1983 54AC11074. . . J PACKAGE 74AC11074. . . D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout


    OCR Scan     		54AC11074 74AC11074 D2957, 500-mA 300-mil PDF

    d204d

    Abstract: No abstract text available
    Text: 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS101 - D3420, FEBRUARY 1990 - REVISED APRIL 1993 i * Contains Eight D-Type Flip-Flops * Clock Enable Latched to Avoid False Clocking DW OR NT PACKAGE TOP VIEW * Applications Include: Buffer/Storage Registers, Shift Registers, Pattern


    OCR Scan     		74AC11377 SCAS101 D3420, 500-mA d204d PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11020,74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES D2957, MAHCH 1987-REVISEDAPRIL1993 54AC11020. . . J PACKAGE 74AC11020. . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise


    OCR Scan     		54AC11020 74AC11020 D2957, 1987-REVISEDAPRIL1993 500-mA 300-mil PDF

    74AC11151

    Abstract: No abstract text available
    Text: 74AC11151 1-0F-8 DATA SELECTOR/MULTIPLEXER D3348, JUNE 1989 - REVISED APRIL 1993 * 8-Llneto 1-Line Multiplexers Can Perform as Boolean Function Generators, Parallel-to-Serial Converters, or Data Source Selectors □ OR N PACKAGE TOP VIEW DO [ 1 OË[ 2 Y [ 3


    OCR Scan     		74AC11151 D3348, 500-mA 300-mll PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957. JUNE 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Pertormance Implanted CMOS 1-^m Process


    OCR Scan     		54AC11030, 74AC11030 D2957. 1987-R 500-mA 300-mll S4AC11032-85 54AC11030 D2957, PDF