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    74S112 Search Results

    74S112 Result Highlights (1)

    Part ECAD Model Manufacturer Description Download Buy
    SN74S112AN Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
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    74S112 Price and Stock

    Rochester Electronics LLC SN74S112ANSR

    IC FF JK TYPE DUAL 1BIT 16SO
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    Rochester Electronics LLC SN74S112AN3

    J-K FLIP-FLOP
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    Rochester Electronics LLC SN74S112ADR

    IC FF JK TYPE DUAL 1BIT 16SOIC
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    Rochester Electronics LLC SN74S112AN

    SN74S112A DUAL J-K NEGATIVE-EDGE
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    Texas Instruments SN74S112AN

    IC FF JK TYPE DUAL 1BIT 16DIP
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    DigiKey SN74S112AN Tube 192 1
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    Component Electronics, Inc SN74S112AN 2,575
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    74S112 Datasheets (7)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74S112 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74S112 Signetics Dual J-K Edge-Triggered Flip-Flop Scan PDF
    74S112 Signetics Dual J-K Edge Triggered Flip-Flop Scan PDF
    74S112 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74S112DC Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    74S112FC Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    74S112PC Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF

    74S112 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74S112

    Abstract: 54 dual JK fairchild
    Text: Revised April 2000 74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and


    Original     		PDF DM74S112 29-JUL-00) ////roarer/root/data13/imaging/BIT. 04/08032000/FAIR/08022000/DM74S112 DM74S112N DM74S112N DM74S112CW 74S112 54 dual JK fairchild

    pj 56 diode

    Abstract: pj 34 diode S112 ECG74 S114 74LS 74S112 74S113 74S114 ECG74S74
    Text: S y lv a n ia ECG S e m ic o n d u c to rs ECG74S74, 74S112, 74S113, 74S114 Dual Flip/Flops M a x R a t i n g s / O p e r a t i n g C o n d itio n s 14 13 74H 74 R A T IN G S S E R IE S S E R IE S M ax im u m A llow able D IO D E 74S H 10 9 6 •2 8 0 " 7 . II


    OCR Scan     		PDF ECG74S74, 74S112, 74S113, 74S114 ECG74S74-" pj 56 diode pj 34 diode S112 ECG74 S114 74LS 74S112 74S113 74S114 ECG74S74

    Untitled

    Abstract: No abstract text available
    Text: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs


    OCR Scan     		PDF 54S/74S112 4LS/74LS112 54/74LS 54/74S

    3S114

    Abstract: 74S112
    Text: Sylvan ia ECG Sem ico nd ucto rs ECG74S74, 74S112, 74S113, 74S114 Dual Flip/Flops M ax R atings/O perating Conditions 74H 74 R A T IN G S S E R IE S M aximum Allowable 14 13 12 S E R IE S 7 7 4 LS S E R IE S D IO D E E M IT T E R IN PU T S IN PU TS 7 7 7 74S


    OCR Scan     		PDF ECG74S74, 74S112, 74S113, 74S114 3S114 74S112

    74S112

    Abstract: 54S112 ScansUX1001
    Text: FAIRCHILD SUPER HIGH SPEED TTL/SSI • 9S112/54S112, 74S112 DUAL JK EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The 9S112/54S 112, 74S112 dual J K flip -flo p s feature individual J, K, clock, and asynchronous preset and clear inputs to each flip -flo p . When the clock goes H IG H , the inputs are enabled and data w ill be accepted. The logic level o f the J and K inputs may be


    OCR Scan     		PDF 9S112/54S112, 74S112 54S112 ScansUX1001

    8 pin dip j k flipflop ic

    Abstract: 74LS112P 74LS112D 74LS112PC 74ls112 pin diagram
    Text: NATIONAL SEMICOND {LOGIC} DEE D | b S O H E E • 00b37fl7 S | 112 T-lk-07-0 7 CO NN ECTIO N DIAGRAM PINOUT A 54S/74S112 54LS/74LS112 CPi DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP


    OCR Scan     		PDF 00b37fl7 T-lk-07-0 54S/74S112 54LS/74LS112 54/74S 54/74LS 8 pin dip j k flipflop ic 74LS112P 74LS112D 74LS112PC 74ls112 pin diagram

    74LS112P

    Abstract: 74LS112D 74ls112 pin diagram 74LS112PC 74LS112 74s112p 74LS112DC 54S112DM 74LS112F 74S112
    Text: 112 C O N N E C T IO N D IA G R A M P IN O U T A /54S/74S112 ö ^ \yt4LS/74LS112 b / / c o t , cpi DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP IN PU TS O U TPU T @ tn @ tn + 1 J K Q L L H H L H L H L H Co Q Ü J c d , So Q T « ]c d 2 £ S d ì [4 tT| cp 2 Qi T


    OCR Scan     		PDF /54S/74S112 \/54LS/74LS112 54/74LS 54/74S S4/74LS 74LS112P 74LS112D 74ls112 pin diagram 74LS112PC 74LS112 74s112p 74LS112DC 54S112DM 74LS112F 74S112

    74S206

    Abstract: 74s201
    Text: 54/74S ELECTRICAL CHARACTERISTICS See Notes - Page 50 INPUT VOLTAGE V|L (V) PARAMETER TEST CONDITIONS LOW LEVEL VÇC~MIN MIN TYP MAX OUTPUT VOLTAGE V|C(V) V|H (V) HIGH LEVEL CLAMP VOLTAGE V çç= M IN VCC = “ IN l|=-18 mA MIN TYP MAX MIN TYP VOH (V) HIGH LEVEL


    OCR Scan     		PDF 54/74S 54/74S00 54/74S02 54/74S03 54/74S04 54/74S05 54/74S260 54/74S280 54/74S301 74S206 74s201

    dy 255

    Abstract: 74s405 H R C M F 2J 225 Fairchild 9960 nixie driver 9614 line driver ci 8602 gn block diagram FJH211 Fairchild msi cul9960 variable frequency circuit diagram using IC 555
    Text: IN THE, BOSTON - 6 17- 4 4 * A SUBSIDiA) ./ OF DUCOMMUN INCORPOfiATED S, MASS vw . JU N E 1 97 S Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the


    OCR Scan     		PDF

    MH1SS1

    Abstract: TESLA mh 7400 MH 7404 mh 7400 tesla cdb 838 tda 7851 L 741PC TDB0124DP tda 4100 TDA 7851 A
    Text: m ö lk ^ o e le l-c te n a n il-c Information Applikation RGW Typenübersicht Vergleich Teil 2: RGW M iM U Z A U l KÉD lnrüÖC=SraO Information Applikation HEFT 50 RGW Typenübersicht + Vergleich Teil 2: RGW wob Halbleiterwerk Frankfurt /oder bt r iab im v«b kombinat mikrootektronik


    OCR Scan     		PDF

    D 8243 HC

    Abstract: SO3A 6164 ram rb1-e N74S00 ITT301 N74S04 B177 55604A CD 5888
    Text: Signetics Integrated Circuits Schottky T T L Schottky T T L 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith


    OCR Scan     		PDF N74S00N 55376D N74S02N 55377B N74S03N 55378X N74S04N 55379R N74S05N 5380A D 8243 HC SO3A 6164 ram rb1-e N74S00 ITT301 N74S04 B177 55604A CD 5888

    7472 PIN DIAGRAM

    Abstract: 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 A 4 — J. 9— 10 So « Q — 2 J U» CP o 1— CD 0—3 ¿ So Q CP 8_ K Ä Q Co —I I_ Vcc = Pin 14 GND = Pin 7 in Ü Q UJ EDGE-TRIGGERED 9 O (9 D58 54H/74H106 D59b 54H/74H108


    OCR Scan     		PDF 54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54H/74H73 54H/74H103 54S/74S113 7472 PIN DIAGRAM 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476

    74ls112 pin configuration

    Abstract: 74ls112 function table 74LS112 74S112
    Text: Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,


    OCR Scan     		PDF 74LS112, 1N916, 1N3064, 500ns 500ns 74ls112 pin configuration 74ls112 function table 74LS112 74S112

    74s112n

    Abstract: 54S112 74S112
    Text: I R C H I L D S E M I C O N D U C T O R TM 74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description sition tim e of th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock


    OCR Scan     		PDF DM74S112 74s112n 54S112 74S112

    74IS04

    Abstract: crt controller 6845 74S393 faraday xt 74IS74 74IS00 6845e crt controller 74832 block diagram of 74LS138 3 to 8 decoder
    Text: 3486347 FARADAY 84D 00245 ELECTRONICS CORP ELECTRONICS INC 04 DEÌ MONOCHROME DISPLAY CONTROLLER FARADAY FE2200 FEATURES: Generates the CRT Display Controller Clock and Other Timing Signals Uses a Crystal or a TTL Signal for Frequency Source Incorporates Complete


    OCR Scan     		PDF FE2200 -33-Cfj FE2200_ T-5Z-33- FE2200 74IS04 crt controller 6845 74S393 faraday xt 74IS74 74IS00 6845e crt controller 74832 block diagram of 74LS138 3 to 8 decoder

    74ls112 pin diagram

    Abstract: 74LS112 74ls112 pin configuration 74ls112 function table 74ls112 waveform 74LS 74S112 N74LS112D N74LS112N N74S112D
    Text: 74LS112, S112 S ig n e tic s Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Lo gic P roducts DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set 3d and Reset (Rq) inputs, when LOW,


    OCR Scan     		PDF 74LS112, 1N916, 1N3064, 500ns 74ls112 pin diagram 74LS112 74ls112 pin configuration 74ls112 function table 74ls112 waveform 74LS 74S112 N74LS112D N74LS112N N74S112D

    74LS115

    Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
    Text: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25


    OCR Scan     		PDF

    itt 7441

    Abstract: transistor fcs 9012 7446 BCD to 7-segment Fairchild dtl catalog Truth Table 74192 7400 quad 2-input NAND gate truth-table 7449 BCD to 7-segment 7483 truth table Motorola Diode 54H01 semiconductors cross reference
    Text: TTL DATA BOOK Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the Numerical Index. If you are trying to choose the best device for your application, consult the


    OCR Scan     		PDF APP-161 1-of-16 12-lnput itt 7441 transistor fcs 9012 7446 BCD to 7-segment Fairchild dtl catalog Truth Table 74192 7400 quad 2-input NAND gate truth-table 7449 BCD to 7-segment 7483 truth table Motorola Diode 54H01 semiconductors cross reference

    SN74ALS123

    Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
    Text: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS


    OCR Scan     		PDF MIL-M-38510 SN74ALS123 SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138

    dm8130

    Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
    Text: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408


    OCR Scan     		PDF 54H00 54L00 54LS00 54H01 54L01 54LS01 54L02 54LS02 54L03 54LS03 dm8130 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76

    DM74367

    Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
    Text: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,


    OCR Scan     		PDF

    SN7449

    Abstract: 54175 SN7401 74L42 SN7437 SN74S40
    Text: Ordering Instructions and Mechanical Data INTEGRATED CIRCUITS MECHANICAL DATA ORDERING INSTRUCTIONS Electrical characteristics presented in this catalog, unless otherwise noted, apply for circuit type s listed in the page heading regardless of package. Except for diode arrays, ECL, and MOS devices, the availability of a circuit function in a


    OCR Scan     		PDF SN15312 SN15325, SN15370 SN7449 54175 SN7401 74L42 SN7437 SN74S40

    BPW22A

    Abstract: cm .02m z5u 1kv pin configuration of BFW10 la4347 B2X84 TDA3653 equivalent TRIAC TAG 9322 HEF40106BP equivalent fx4054 core dsq8
    Text: Contents Page Page New product index Combined index and status codes viii x Mullard approved components BS9000, CECC, and D3007 lists CV list Integrated circuits Section index xliii 1 5 Standard functions LOGIC FAMILIES CMOS HE4000B family specifications CMOS HE4000B family survey


    OCR Scan     		PDF BS9000, D3007 HE4000B 80RIBUTION BS9000 BPW22A cm .02m z5u 1kv pin configuration of BFW10 la4347 B2X84 TDA3653 equivalent TRIAC TAG 9322 HEF40106BP equivalent fx4054 core dsq8

    54s112

    Abstract: 74LS112A 74S112
    Text: SN54LS112A, SN54S112, SN74LS112A. 74S112A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR _ Fully Buffered to Offer Maximum Isolation from External Disturbance • D 2 6 6 1 . A P R IL 1 9 8 2 - R E V I S E D M A R C H 1 9 8 8


    OCR Scan     		PDF SN54LS112A, SN54S112, SN74LS112A. SN74S112A 54S112, 54s112 74LS112A 74S112