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    Nexperia 74AVC16835ADGG,112

    Bus XCVR Single 18-CH 3-ST 56-Pin TSSOP Tube (Alt: 74AVC16835ADGG,112)
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    Avnet Silica 74AVC16835ADGG,112 54 Weeks 35
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    Nexperia 74AVC16835ADGG,118

    Bus XCVR Single 18-CH 3-ST 56-Pin TSSOP T/R (Alt: 74AVC16835ADGG,118)
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    Avnet Silica 74AVC16835ADGG,118 54 Weeks 2,000
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    74AVC16835ADGG Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74AVC16835ADGG Philips Semiconductors 18 Bit Registered Driver with Dynamic Controlled Outputs (3-State) Original PDF
    74AVC16835ADGG Philips Semiconductors Register, Single, 18 Channel, Non-Inverting, CMOS, 56-TSSOP Original PDF
    74AVC16835ADGG,112 NXP Semiconductors 18-bit registered driver with Dynamic Controlled Outputs (3-State) - Description: 1.8/2.5V 18-Bit Registered Driver (3-State) ; Logic switching levels: CMOS ; Number of pins: 56 ; Output drive capability: Medium ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2 ns; Voltage: Low; Package: SOT364-1 (TSSOP56); Container: Tube Original PDF
    74AVC16835ADGG,118 NXP Semiconductors 18-bit registered driver with Dynamic Controlled Outputs (3-State) - Description: 1.8/2.5V 18-Bit Registered Driver (3-State) ; Logic switching levels: CMOS ; Number of pins: 56 ; Output drive capability: Medium ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2 ns; Voltage: Low; Package: SOT364-1 (TSSOP56); Container: Reel Pack, SMD, 13" Original PDF

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    74AVC16835A

    Abstract: 74AVC16835ADGG 74AVC16835ADGV CBT16292 PCK2509S PCK2510S PC133 registered reference design
    Text: INTEGRATED CIRCUITS 74AVC16835A 18-bit registered driver with Dynamic Controlled Outputs 3-State Product data Supersedes data of 2000 Jul 25 Philips Semiconductors 2002 Mar 15 Philips Semiconductors Product data 18-bit registered driver with Dynamic Controlled Outputs (3-State)


    Original     		PDF 74AVC16835A 18-bit 74AVC16835A 74AVC16835ADGG 74AVC16835ADGV CBT16292 PCK2509S PCK2510S PC133 registered reference design