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    74191, 74193 Search Results

    74191, 74193 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    ic 74138

    Abstract: IC 7402, 7404, 7408, 7432, 7400 ic 74139 IC 74147 IC 74373 74148 IC IC 74374 ic 7408, 7432, 7404, 7400, 7433, 7486, 74266 IC 74245 74189
    Text: LEAPER-1 HANDY DIGITAL IC TESTER Supported Devices Features EMC Standards 1.Easy-operating Tester, particularly per 89/336/EEC be designed for the Digital IC 2.Supported Device : 74 / 40 / 45 / 41 / 44 Serial. 3.Small, portable, light and powersaving, usable with batteries.


    Original     		89/336/EEC 34kgs 5000m EN50081-1 EN50082-1 EN55022 IEC801-2 EN60555-210 40H78 ic 74138 IC 7402, 7404, 7408, 7432, 7400 ic 74139 IC 74147 IC 74373 74148 IC IC 74374 ic 7408, 7432, 7404, 7400, 7433, 7486, 74266 IC 74245 74189 PDF

    ic 74192

    Abstract: 74193 application diagrams of IC 74191 ic 74193 74192 ic IC 7419 Ic 74191 of IC 74193 2SA1344 CPH5514
    Text: Ordering number : ENN7419 CPH5514 PNP Epitaxial Planar Silicon Transistor CPH5514 Switching Applications with Bias Resistance Features 0.15 0.2 4 3 0.05 0.6 • [CPH5514] 2.9 0.6 • On-chip bias resistance (R1=10kΩ, R2=10kΩ). unit : mm Composite type with 2 transistors contained in the


    Original     		ENN7419 CPH5514 CPH5514] CPH5514 2SA1344, ic 74192 74193 application diagrams of IC 74191 ic 74193 74192 ic IC 7419 Ic 74191 of IC 74193 2SA1344 PDF

    FZH115B

    Abstract: fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104
    Text: Digital I.C.s, 74INTEGRATED CIRCUITS DIGITAL TTL, 74LS & 74HC Series Quad 2-input NAND gate Quad 2-input NAND gate, open collector Quad 2-input NOR gate Quad 2-input NOR gate, open collector Hex inverter Hex inverter, O/C collector Hex inverter, Buffer 30V O/P


    Original     		74INTEGRATED Line-to-10 150ns 16-DIL 150ns 18-pin 250ns 300ns FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 FZH205 Multiplexer IC 74151 FZH265B 74LS104 PDF

    ic 74193

    Abstract: IC 7419 Ic 74191 2SA1344 CPH5514 CPH5
    Text: 注文コード No. N 7 4 1 9 CPH5514 三洋半導体データシート N CPH5514 特長 PNP エピタキシャルプレーナ形シリコン複合トランジスタ スイッチング用 バイアス抵抗内蔵 ・バイアス抵抗内蔵 (R1=10kΩ, R2=10kΩ)。


    Original     		CPH5514 CPH5514 2SA1344 IT05311 IT05313 IT05368 ic 74193 IC 7419 Ic 74191 2SA1344 CPH5 PDF

    IC TTL 7432

    Abstract: IC 7402, 7404, 7408, 7432, 7400 ttl 74118 74189 memory ic 74138 74189 ttl memory TTL 74289 RC4458 IC 74373 ttl 74592
    Text: Test and Measurement Systems Electronic Manufacturing Services ABI Electronics Limited Dodworth Business Park Barnsley S75 3SP South Yorkshire United Kingdom Tel: +44 0 1226 207420 Fax: +44 (0)1226 207620 www.abielectronics.co.uk ChipMaster Compact Professional IC List


    Original     		LM7808 LM7905 MAX667 MAX872 MAX874 REF02 REF03 REF05 REF43 TLE2425 IC TTL 7432 IC 7402, 7404, 7408, 7432, 7400 ttl 74118 74189 memory ic 74138 74189 ttl memory TTL 74289 RC4458 IC 74373 ttl 74592 PDF

    ic 74193

    Abstract: IC 7419 Ic 74191 2SA1344 CPH5514 N7419
    Text: 注文コード No. N 7 4 1 9 CPH5514 N7419 22004 新 CPH5514 特長 PNP エピタキシャルプレーナ形シリコン複合トランジスタ スイッチング用 バイアス抵抗内蔵 ・バイアス抵抗内蔵 (R1=10kΩ, R2=10kΩ)。 ・従来の CPH にトランジスタを 2 素子内蔵した複合タイプであり実装基板効率が大幅にアップできる。


    Original     		CPH5514 N7419 CPH5514 2SA1344 IT05311 IT05313 IT05368 ic 74193 IC 7419 Ic 74191 2SA1344 N7419 PDF

    74LS190 PIN diagram

    Abstract: presettable digital clock ttl 74191 Fairchild 74190 74LS191 74155 D130 74192 74ls192 pin diagram of 74163
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 TTTT 12 11 10 9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8


    OCR Scan     		74LS190 74LS191 93L21, 54/74S139, 54LS/74LS139 54LS/74LS155 54LS/74LS156 93L01, 93L34, 54LS/74LS259 74LS190 PIN diagram presettable digital clock ttl 74191 Fairchild 74190 74LS191 74155 D130 74192 74ls192 pin diagram of 74163 PDF

    7483 4 bit binary full adder

    Abstract: 74151 demultiplexer 74153 full adder 74198 shift register 7483 4 bit binary adder 7483 8 bit binary adder 74155 demultiplexer 74150 multiplexer bcd adder with 74283 4 bit 7483 binary adder
    Text: Digital Circuits 54/74 MSI Series Type Description Prop Delay ns or Max. Op. Freq. (MHz) Available Packages P w r1 Diss (mW) 14 Pin DC CJ 16 Pin CL 54/7442 BCD-to-Decimal Decoder 22 140 X 54/7443 Excess 3-to-Decimal Decoder 22 X X 54/7444 Excess 3 Gray-to-Decimal Decoder


    OCR Scan     		16-to-1 Types--55Â 7483 4 bit binary full adder 74151 demultiplexer 74153 full adder 74198 shift register 7483 4 bit binary adder 7483 8 bit binary adder 74155 demultiplexer 74150 multiplexer bcd adder with 74283 4 bit 7483 binary adder PDF

    74LS190 pins

    Abstract: 74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins Synchronous 74163 74LS161 74160 74LS162 74LS191 pins
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L-T T L D121 54/7490A, 54LS/74LS90 D122 54/7492, 74LS92 D123 S4/74293, 54LS/74LS293 6 7 141 Vcc = Pin 5 GND = Pin 10 N C = Pin 4,13 - Vcc = Pin 5 GND = Pin 10 N C = 2, 3, 4, 13 D124 S4/7493A, 54LS/74LS93 D125 54/74176, 54/74177,


    OCR Scan     		54/7490A, 54LS/74LS90 74LS92 S4/74293, 54LS/74LS293 S4/7493A, 54LS/74LS93 93L10, 93S10, 93L16, 74LS190 pins 74LS192 PIN diagram 74LS183 TTL 74ls163 74LS192 pins Synchronous 74163 74LS161 74160 74LS162 74LS191 pins PDF

    74LS160

    Abstract: Synchronous 74163 74LS190 pins 74192 74LS193 74LS192 pins 74LS191 pins Fairchild 74190 D129 93S16
    Text: FAIRCHILD DIGITAL TTL I Max Clock Rate MHz Typ Clock to Q Output Delay-ns (Typ) Power Dissipation mW (Typ) Logic/Connection Diagram Package(s) 1 Synchronous 93L16 16 Presettable S _r 23 26 85 D127 4L,7B,9B 2 \/ Synchronous 93S16 1/ 16 Presettable S _r 90


    OCR Scan     		93L16 93S16 54LS/74LS160 54LS/74LS161 54LS/74LS162 54LS/74LS163 54LS/74LS168 54LS/74LS169 54LS/74LS192 54LS/74LS193 74LS160 Synchronous 74163 74LS190 pins 74192 74LS193 74LS192 pins 74LS191 pins Fairchild 74190 D129 PDF

    74162

    Abstract: D129 74LS191 74192 pin diagram of 74163 74160 pin 74190 74LS162 74LS190 pins presettable digital clock
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| FI j j j SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI lil LiJ Lil LiTIU LzJ LlI üü bsJ QNO 9 3 4 5 D85 54LS/74LS373


    OCR Scan     		54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS163 54LS/74LS168 74162 D129 74LS191 74192 pin diagram of 74163 74160 pin 74190 74LS162 74LS190 pins presettable digital clock PDF

    Untitled

    Abstract: No abstract text available
    Text: Digital Circuits 54/74 MSI Series Type Description Prop Delay ns or Max. Op. Freq. (M H z ) Available Packages P w r1 Diss (mW) 14 Pin DC CJ 16 Pin CL DD 54/7442 BC D -to-D e cim al Decoder 22 140 X X 54/7443 Excess 3-to-Decim al Decoder 22 140 X X X 54/7444


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    STR W 5453 A

    Abstract: STR 5453 STR W 5453 STR W 5453 C Truth Table 74190 Truth Table 74192 74193 truth table truth table 7454 str w c 5453 Truth Table 74193
    Text: TTL/MSI 9393/5493, 7493 4 -B IT BINARY COUNTER D E S C R IP T IO N -T h e T T L /M S I 9393/5 4 9 3 , 7493 is a 4-Bit Binary Counter consisting of four master/ slave flip-flops which are internally interconnected to provide a divide-by-two counter and a divide-by-eight counter. A gated direct reset line is provided which inhibits the count inputs and


    OCR Scan     		74H00 STR W 5453 A STR 5453 STR W 5453 STR W 5453 C Truth Table 74190 Truth Table 74192 74193 truth table truth table 7454 str w c 5453 Truth Table 74193 PDF

    7408 CMOS

    Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 74106 CMOS 4017 series ttl 74395
    Text: KG10000 SERIES SEMI-CUSTOM CMOS GATE ARRAY CMOS SILOCON GATE ARRAY Th e KG10000 S e rie s is c o n sists o f s ilico n gate C M O S arrays w hose inte rco n n e ctio n are in itia lly u n s p e c ifie d , th e re fo re custom LSI is p ro ce sse d w ith o n ly one m ask ste p a cu sto m ize d m etal m ask a c c o rd ­


    OCR Scan     		KG10000 7408 CMOS TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 74106 CMOS 4017 series ttl 74395 PDF

    TTL 74139

    Abstract: 74153 mux MSI 74148 16cudslr CI 74138 sn 74373 8mcomp 7404 7408 7432 7408, 7404, 7486, 7432 Flip-Flop 7471
    Text: PLSLIB-TTL /$ ^ n^ X LIBRARY • TTL MacroFunction Library Diskette. • ADLIB, Altera Design Librarian Diskette. To increase design ease and productivity Altera has created M acroFunctions. These are high level building blocks that allow the user to design at


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    asynchronous 4bit up down counter using jk flip flop

    Abstract: counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MH 74151 counter 74169 74169 SYNCHRONOUS 4-BIT BINARY COUNTER
    Text: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T his series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/


    OCR Scan     		MSM70V000 MSM70V000, asynchronous 4bit up down counter using jk flip flop counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MH 74151 counter 74169 74169 SYNCHRONOUS 4-BIT BINARY COUNTER PDF

    IC 7402, 7404, 7408, 7432, 7400

    Abstract: 7408, 7404, 7486, 7432 CI 74122 ci 7445 CI 7442a ci 74174 7402, 7404, 7408, 7432, 7400 LM 7408 lm 7486 IC 7444
    Text: 54/74 ELECTRICAL CHARACTERISTICS See Notes - Page 50 INPUT VOLTAGE V|L (V) LOW LEVEL PARAMETER V|H (V ) HIGH LEVEL OUTPUT VOLTAGE V|C (V) CLAMP VOLTAGE VOL (V) LOW LEVEL INPUT CURRENT VO H(V) HIGH LEVEL l,L (mA) LOW LEVEL VCC=MIN V|N=* TEST CONDITIONS Vc c ^ M IN


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    74191, 74192, 74193 circuit diagram

    Abstract: IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411
    Text: P L S -W S /H P MAX+PLUS II Programmable Logic Software for HP/Apollo Workstations Data Sheet September 1991, ver. 3 Features □ □ LI LI □ □ □ □ General Description Software support for Classic, M A X 5000, M A X 7000, and ST G E P L D s Runs on H ew lett Packard /A p o llo Series 3000, 3500, 4000, 4500, and


    OCR Scan     		HP400 QIC-24, 60-Mbytetape 74191, 74192, 74193 circuit diagram IC 7402, 7404, 7408, 7432, 7400 Truth Table 74161 counter schematic diagram 74161 7408, 7404, 7486, 7432 74244 uses and functions counter 74168 74191, 74192, 74193 truth table of ic 7495 A schematic diagram for the IC of 7411 PDF

    truth table for ic 74138

    Abstract: 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
    Text: PLCAD-SUPREME & PLS-SUPREME A+PLUS Programmable Logic Development System & Software Data Sheet September 1991, ver. 1 Features J J J J □ □ H igh-level su p p o rt for A ltera's general-purpose Classic EPLDs M ultiple design entry m ethods LogiCaps schem atic capture


    OCR Scan     		44-Mbyte, 386-based truth table for ic 74138 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table PDF

    74139 demultiplexer

    Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER pin diagram 41 multiplexer 74153 3-8 decoder 74138 pin diagram bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 CI 74151 74181 74175 clock 74165 block diagram 74151 demultiplexer
    Text: M OIVIOUOUU, s em i c onductor GENERAL DESCRIPTION FEATURES The OKI MSM60300, MSM60700. and MSM61000 gate arrays are fabricated using state-of-the-art 3/i dual-layer metal silicon gate CMOS technology. A unit cell consists of 4 pairs o f transistors where each pair is made up of a PMOS and a NMOS transistor.


    OCR Scan     		MSM60300, MSM60700, MSM61000 MSM60300. MSM60700. MSMC0300 MSM60700 MSM61000 74139 demultiplexer 74169 SYNCHRONOUS 4-BIT BINARY COUNTER pin diagram 41 multiplexer 74153 3-8 decoder 74138 pin diagram bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 CI 74151 74181 74175 clock 74165 block diagram 74151 demultiplexer PDF

    7486 XOR gate

    Abstract: 8mcomp XOR 7486 Truth Table 74192 4count XOR 7486 GATE 16cudslr 7472 truth table 7486 xor 74194 truth table
    Text: PROGRAMMABL E a \ l o g ic s o f t w a r e I-WV i1 I— rT -U U PLS-MAX =Er - ]T — n V n i n ni l A V P L S -m A X MAX+PLUS FEATURES GENERAL DESCRIPTION • Unified Development system for the entire Multiple Array Matrix MAX family of EPLDs. • Multiple design entry methods including a hier­


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    IC AND GATE 7408 specification sheet

    Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
    Text: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format


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    74139 for bcd to excess 3 code

    Abstract: design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 jk flip flop to d flip flop conversion alu 74381 74541 buffer design excess 3 counter using 74161 two 3 to 8 decoders 74138 7444 series Excess-3-gray code to Decimal decoder
    Text: • G E N E R A L D ESCRIPTIO N T h e M S M 7 0 H 0 0 0 series is the gate array L S I based on the m aster slice m ethod using the high perfo rm an ce silico n gate 2 m icro n H C M O S process w ith the d u al-layer m etal s tru ctu re . T h is series has the featu res to ea sily realize fu n c tio n s o f the sch m itt trig ger, c ry s ta l/


    OCR Scan     		MSM70H000 MSM70H000, 74139 for bcd to excess 3 code design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 jk flip flop to d flip flop conversion alu 74381 74541 buffer design excess 3 counter using 74161 two 3 to 8 decoders 74138 7444 series Excess-3-gray code to Decimal decoder PDF

    sn 74373

    Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
    Text: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher


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