GSP2E-7401
Abstract: sirf grf2i GSP2E GSP2e-7400 GSP2E7410 7400 series pin connection grf1/lx grf2i ADC7810 TTL 7410
Text: This document becomes an UNCONTROLLED COPY once printed from SiRF’s Intranet. To receive a controlled copy, please contact Document Control. SiRF Application Note GSP2e Hardware Implementation Document Number APNT0012 Revision 1.1 5/16/2000 Author: Oded Yossifor
|
Original
|
PDF
|
APNT0012
GSP2E-7401
sirf grf2i
GSP2E
GSP2e-7400
GSP2E7410
7400 series pin connection
grf1/lx
grf2i
ADC7810
TTL 7410
|
Untitled
Abstract: No abstract text available
Text: SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SDAS187A – APRIL 1982 – REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
|
Original
|
PDF
|
SN54ALS00A,
SN54AS00,
SN74ALS00A,
SN74AS00
SDAS187A
300-mil
SN54AS00
SN74AS00
|
74151 PIN DIAGRAM
Abstract: 74151 22v10 5192JM CY7C340 PRODUCT CHANGE PALC22V10B programmer EPLD CY7C340 CY7C341B CY7C342B
Text: 40 EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase
|
Original
|
PDF
|
CY7C340
CY7C34X)
65-micron
CY7C34XB)
74151 PIN DIAGRAM
74151
22v10
5192JM
CY7C340 PRODUCT CHANGE
PALC22V10B
programmer EPLD
CY7C341B
CY7C342B
|
C3402
Abstract: 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C CY7C340
Text: EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase
|
Original
|
PDF
|
CY7C340
CY7C34X)
65-micron
CY7C34XB)
C3402
74151
5128LC-1
74151 PIN DIAGRAM
5128LC-2
74151 8 to 1
74151 pin connection
function of 74151
22V10-10C
|
74151 waveform
Abstract: CY7C340 5128LC 7C340 programming 7C340 CY7C341B CY7C342B CY7C344 CY7C346 FLASH370
Text: 7c340: 12-13-90 Revision: October 19, 1995 CY7C340 EPLD Family Multiple Array Matrix HighĆDensity EPLDs called expander product terms. These exĆ Ċ VHDL simulation ViewSimt Ċ Available on PC and Sun platforms panders are used and shared by the macroĆ
|
Original
|
PDF
|
7c340:
CY7C340
35aproductmacrocell.
74151 waveform
5128LC
7C340 programming
7C340
CY7C341B
CY7C342B
CY7C344
CY7C346
FLASH370
|
74151
Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer
Text: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of
|
Original
|
PDF
|
CY7C340
CY7C34X)
65-micron
CY7C34XB)
74151
74151 pin connection
C3406
74151 PIN DIAGRAM
74151 waveform
counter schematic diagram 74161
programmer EPLD
22v10
5192JM
74151 multiplexer
|
PC8245
Abstract: PowerPC 603r RISC Microprocessor Manual PC603R 740P, 255 CBGA and CI-CGA packages cga motorola PPC12 PC106 PC755 360-Pin PC740P
Text: Host Processors Integrated Processors & Peripherals Communication Controllers Product Family Overview Specific Products & Services PPC1201. ppt - 1 PowerPC PowerPC Microprocessor Microprocessor Family Family Strategy Strategy ATMEL-Grenoble is proposing a wide range of
|
Original
|
PDF
|
PPC1201.
21-years'
MIL-STD-883,
PC8245
PowerPC 603r RISC Microprocessor Manual
PC603R
740P, 255 CBGA and CI-CGA packages
cga motorola
PPC12
PC106
PC755
360-Pin
PC740P
|
SN54LS00J
Abstract: JM38510/30001BCA snj54ls00j 30001bca 74LS00 gate diagram nand sn7400
Text: SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 D Package Options Include Plastic Small-Outline D, NS, PS , Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and
|
Original
|
PDF
|
SN5400,
SN54LS00,
SN54S00
SN7400,
SN74LS00,
SN74S00
SDLS025B
SN5400
SN54S00
SN54LS00J
JM38510/30001BCA
snj54ls00j
30001bca
74LS00 gate diagram nand
sn7400
|
msl 9350
Abstract: TTL SN7400N SN7400N SN7400P 7400 functional cross-reference TEXAS INSTRUMENTS SN7400N ttl nand gate 7400 quad
Text: SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003 D Package Options Include Plastic Small-Outline D, NS, PS , Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and
|
Original
|
PDF
|
SN5400,
SN54LS00,
SN54S00
SN7400,
SN74LS00,
SN74S00
SDLS025B
SN5400
SN54S00
msl 9350
TTL SN7400N
SN7400N
SN7400P
7400 functional cross-reference
TEXAS INSTRUMENTS SN7400N
ttl nand gate 7400 quad
|
Untitled
Abstract: No abstract text available
Text: STM32F102x8 STM32F102xB Medium-density USB access line, ARM-based 32b MCU with 64/128KB Flash, USB FS, 6 timers, ADC & 8 com. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M3 CPU – 48 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
|
Original
|
PDF
|
STM32F102x8
STM32F102xB
64/128KB
32-bit
4-to-16
DocID15056
|
Untitled
Abstract: No abstract text available
Text: STM32F102x4 STM32F102x6 Low-density USB access line, ARM-based 32-bit MCU with 16/32 KB Flash, USB FS, 5 timers, ADC & 5 com. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M3 CPU – 48 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
|
Original
|
PDF
|
STM32F102x4
STM32F102x6
32-bit
4-to-16
DocID15057
|
IL028
Abstract: STM32F102T8 stm32f102xx stm32 encoder stm32f102 manual IL 028
Text: STM32F102x8 STM32F102xB Medium-density USB access line,ARM-based 32b MCU with 64/128KB Flash,USB FS interface,6 timers, ADC&8 com. interfaces Datasheet − production data Features • Core: ARM 32-bit Cortex -M3 CPU – 48 MHz maximum frequency, 1.25 DMIPS/MHz Dhrystone 2.1
|
Original
|
PDF
|
STM32F102x8
STM32F102xB
64/128KB
32-bit
4-to-16
IL028
STM32F102T8
stm32f102xx
stm32 encoder
stm32f102 manual
IL 028
|
10 band graphic equalizer LM835
Abstract: lm835 FSA2619 FSA2619P LMC35 lmc835 National Semiconductor AN-140 FSA-2619P TTL 7400 national semiconductor INTEL I7 microprocessor circuit diagram
Text: National Semiconductor Application Note 791 Charlie Mitchell October 1991 INTENT This note describes the implementation and use of a standard memory element in the realization of state machine control for the purpose of generating serial data The applications shown here employ serial data streams to control
|
Original
|
PDF
|
20-3A
10 band graphic equalizer LM835
lm835
FSA2619
FSA2619P
LMC35
lmc835
National Semiconductor AN-140
FSA-2619P
TTL 7400 national semiconductor
INTEL I7 microprocessor circuit diagram
|
70L95
Abstract: 80L95 VC555 DM54365 DM54366 DM54367 DM54368 70L96 80L97
Text: ^ 2 Additional Devices D M 70/D M 8095, L95, 96, L96, 97, L97, 98, L98 TRI-STATE Hex Buffers www .Datasheet. i n General Description These devices provide six, two-input buffers in each pack age. Both the standard 7400 com patible TTL technology, and the “ true tenth-pow er" (74L com patible) low power ver
|
OCR Scan
|
PDF
|
DM70/DM8095,
DM70/80
70L95
80L95
VC555
DM54365
DM54366
DM54367
DM54368
70L96
80L97
|
|
|
7400A
Abstract: B8-11
Text: - PRELIMINARY - March 1995 Edition 3.0 FUJITSU PRODUCT PROFILE SHEET M B 8 1 1 7 4 0 0 A -50/-60/-70 CMOS 4M x 4 BIT FAST PAGE MODE DYNAMIC RAM CMO S 4,194,304 x 4 BIT Fast Page Mode Dynamic RAM The Fujitsu MB8117400A is a fully decoded CM OS Dynamic RAM DRAM that contains
|
OCR Scan
|
PDF
|
MB8117400A
B8117400A
P-DRAM-DS-20099-11/95
7400A
B8-11
|
Untitled
Abstract: No abstract text available
Text: GOULD 4055916 GOUL D IN C / GOULD A M I SEMI CONDUCTOR 03 DIV D • 03E MDSSTlb 1 1494 DQ114TM 0^ TABLE OF CONTENTS SECTION 1: DESIGN INFORMATION 1.1 CHOOSING AN ARRAY. 1-5 1.1.1 Determining Gate Count. 1-6
|
OCR Scan
|
PDF
|
DQ114TM
|
Untitled
Abstract: No abstract text available
Text: CY7C340 EPLD Family CYPRESS SEMICONDUCTOR • Erasable, user-configurable CMOS EPLDs capable o f implementing highdensity custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase performance
|
OCR Scan
|
PDF
|
CY7C340
CY7C34X)
65-micron
CY7C34XB)
1076-compliant
CY3340
CY7C341
CY3340F
CY3342
|
LCA200K
Abstract: 130 nm CMOS standard cell library 10-JK LEA100K CLDCC LEA200K
Text: 5304Û04 ÜD m STl 3bb • LLC LSI LOGIC LEA200K Embedded Array Series Description The LEA200K Embedded Array Series is a submicron HCMOS ASIC product which com bines the integration and performance bene fits of Cell-Based ASICs with the fast turnaround time of Array-Based ASICs. The
|
OCR Scan
|
PDF
|
LEA200K
55-micron
LCA200K
130 nm CMOS standard cell library
10-JK
LEA100K
CLDCC
|
25128LI
Abstract: 5130LC vhdl 74161 5128LC 5192LC
Text: fax id: 6100 p vXpX : v«*1 C Y 7 C 3 4 0 EP L D Fami l y - Multiple Array Matrix High-Density EPLDS tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. Feat ures • E r a s a b l e , u s e r - c o n f i g u r a b l e C M O S E P L D s c a p a b l e of
|
OCR Scan
|
PDF
|
CY7C342B.
25128LI
5130LC
vhdl 74161
5128LC
5192LC
|
EPM5032
Abstract: program EPM5032 ple3-12a PLS-MAX PLDS-MAX altera LP4 74HC
Text: 32 MACROCELL h igh d e n s it y m ax e p ld P P M c r m u u u c FEATURES G EN E R A L D E SC R IP T IO N • Erasable, User-Configurable, High-Density replacement for TTL and 74HC logic. • Advanced 0.8 micron CMOS EPROM technology. • High speed tpd = 20ns and 83MHz clock
|
OCR Scan
|
PDF
|
PIVI5032
83MHz
EPM5032
PLE3-12A
program EPM5032
PLS-MAX
PLDS-MAX
altera LP4
74HC
|
LCA100K
Abstract: LSI LOGIC LCA100K
Text: »• * LSI LOGIC * LCA100K Compacted Array Plus Series Description The LCA100K Compacted A rray Plus Series is an HCMOS Array-Based ASIC ApplicationSpecific Integrated Circuit product offering extremely high performance. The LCA100K Series is manufactured using 1.0-micron
|
OCR Scan
|
PDF
|
LCA100K
LSI LOGIC LCA100K
|
LSI CMOS GATE ARRAY
Abstract: LEA100066 LEA100K LSI LOGIC LEA100K rs flip-flop IC 7400 24008a
Text: LSI LOGIC LEA100K Embedded Array Series Description The LEA100K Embedded Array Series is an HCMOS ASIC Application-Specific Integrated Circuit product which combines the integra tion and performance benefits of Cell-Based ASICs with the fast turnaround time of ArrayBased ASICs. The LEA100K series is manufac
|
OCR Scan
|
PDF
|
LEA100K
LSI CMOS GATE ARRAY
LEA100066
LSI LOGIC LEA100K
rs flip-flop IC 7400
24008a
|
4x4 barrel shifter with flipflop
Abstract: LEA100K LCA100K ta 8259 LEA100006 LEA100008 LSI LOGIC LEA100K 82385 B282 24008A
Text: LSI LOGIC LEA100K Embedded Array Series Description The LEA100K Embedded A rray Series is an HCMOS ASIC A pplication-S pecific Integrated Circuit product w hich combines the integra tion and perform ance benefits of Cell-Based ASICs w ith the fa st turnaround tim e of A rrayBased ASICs. The LEA100K series is m anufac
|
OCR Scan
|
PDF
|
LEA100K
4x4 barrel shifter with flipflop
LCA100K
ta 8259
LEA100006
LEA100008
LSI LOGIC LEA100K
82385
B282
24008A
|
LCA200K
Abstract: re 497.1 82385 sim 300 v 703 LCB007
Text: LSI LOGIC NOV 19 1992 LEA200K Embedded Array Series Description The LEA200K Embedded Array Series is a submicron HCMOS ASIC product w hich com bines the integration and performance bene fits of Cell-Based ASICs w ith the fast turnaround time of Array-Based ASICs. The
|
OCR Scan
|
PDF
|
LEA200K
55-micron
LCA200K
re 497.1
82385
sim 300 v 703
LCB007
|
