LVDS fin 1002
Abstract: BU90RT102 c1005x7r1h222kt GRM155B30G225ME15D Murata grm155r60j225me15d CM05X5R CM05X5R225M04AH GRM155B HSYNC, VSYNC, DE 2NTR
Text: LVDS Interface ICs 70bit LVDS Distributor BU90RT102 No.10057EAT08 ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operates from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times 7X stream and reduce cable number by 3(1/3) or less.
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70bit
BU90RT102
10057EAT08
150MHz
250MHz.
RGB10bits
20135MHz
R1010A
LVDS fin 1002
BU90RT102
c1005x7r1h222kt
GRM155B30G225ME15D
Murata grm155r60j225me15d
CM05X5R
CM05X5R225M04AH
GRM155B
HSYNC, VSYNC, DE
2NTR
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PDF
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Untitled
Abstract: No abstract text available
Text: LVDS Interface ICs 70bit LVDS Distributor BU90RT102 No.13057EBT08 ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operates from 20MHz to 135MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times 7X stream and reduce cable number by 3(1/3) or less.
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Original
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70bit
BU90RT102
13057EBT08
20MHz
135MHz
250MHz.
RGB10bits
135MHz
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PDF
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R25G2
Abstract: No abstract text available
Text: LVDS Interface ICs 70bit LVDS Distributor BU90RT102 No.13057EBT08 ●Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operates from 20MHz to 135MHz wide clock range, and number of bits range is from 35 to 70. Data is transmitted seven times 7X stream and reduce cable number by 3(1/3) or less.
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Original
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70bit
BU90RT102
13057EBT08
20MHz
135MHz
250MHz.
RGB10bits
20135MHz
R1102A
R25G2
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PDF
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DSP48A1
Abstract: DSP48A1 UG389 UG389 XC6SL DSP48A1 post adder XC6SLX150T verilog code for barrel shifter 8 bit carry select adder verilog code verilog code for 16 bit carry select adder systolic multiplier and adder vhdl code
Text: Spartan-6 FPGA DSP48A1 Slice User Guide [optional] UG389 v1.1 August 13, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
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DSP48A1
UG389
DSP48A1 UG389
UG389
XC6SL
DSP48A1 post adder
XC6SLX150T
verilog code for barrel shifter
8 bit carry select adder verilog code
verilog code for 16 bit carry select adder
systolic multiplier and adder vhdl code
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PDF
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CY7C1381B-100AI
Abstract: 381B CY7C1381B CY7C1381B-117AC CY7C1383B
Text: 381B CY7C1381B CY7C1383B 512 x 36/1M × 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10.0 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion
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Original
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CY7C1381B
CY7C1383B
36/1M
CY7C1381B/CY7C1383B
x36/1M
CY7C1381B-100AI
381B
CY7C1381B
CY7C1381B-117AC
CY7C1383B
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PDF
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WCSS1818V1F
Abstract: WCSS1836V1F WCSS1836V1F-QC100
Text: S1836V1F WCSS1836V1F WCSS1818V1F 512 x 36/1M × 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 8.5ns Fast clock speed: 100 MHz Provide high-performance 2-1-1-1 access rate Optimal for depth expansion 3.3V –5% / +10% power supply
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Original
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S1836V1F
WCSS1836V1F
WCSS1818V1F
36/1M
WCSS1836V1F-QC100
100-Lead
WCSS1818V1F-QC100
100-pin
WCSS1818V1F
WCSS1836V1F
WCSS1836V1F-QC100
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PDF
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CY7C1461V25
Abstract: CY7C1463V25 CY7C1465V25
Text: CY7C1461V25 CY7C1463V25 CY7C1465V25 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M x 36/2M × 18/512K × 72 common I/O
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CY7C1461V25
CY7C1463V25
CY7C1465V25
36/2M
18/512K
133-MHz
36/2M
18/512K
150-MHz
CY7C1461V25
CY7C1463V25
CY7C1465V25
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PDF
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CY7C1444V33
Abstract: CY7C1444V33-300AC CY7C1444V33-300BGC CY7C1444V33-300BZC CY7C1445V33 CY7C1445V33-300AC CY7C1445V33-300BGC
Text: CY7C1445V33 CY7C1444V33 PRELIMINARY 1M x 36/2M x 18 Pipelined DCD SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 300, 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.3, 2.7, 3.0, and 3.5 ns
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Original
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CY7C1445V33
CY7C1444V33
36/2M
CY7C1444V33/CY7C1445V33
CY7C1444V33
CY7C1444V33-300AC
CY7C1444V33-300BGC
CY7C1444V33-300BZC
CY7C1445V33
CY7C1445V33-300AC
CY7C1445V33-300BGC
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PDF
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AK4617VQ
Abstract: No abstract text available
Text: [AK4617] AK4617 192kHz 24-bit 2ch/12ch Audio CODEC 1. General Description The AK4617 is a single chip audio CODEC that includes 2-channel ADC and 12-channel DAC. The stereo ADC supports differential/single-ended analog inputs. The high performance 12-channel DAC integrates
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AK4617]
AK4617
192kHz
24-bit
2ch/12ch
AK4617
12-channel
106dB
AK4617.
AK4617VQ
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PDF
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IS61LPS25632T-166TQ
Abstract: IS61LPS25632T-200TQ
Text: ISSI IS61LPS25632T/D/J IS61LPS25636T/D/J IS61LPS51218T/DJ 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINED, SINGLE-CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and
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IS61LPS25632T/D/J
IS61LPS25636T/D/J
IS61LPS51218T/DJ
100-Pin
119-pin
select225Mhz
IS61LPS51218D-225BI
IS61LPS51218D-225TQI
250Mhz
IS61LPS51218D-250B
IS61LPS25632T-166TQ
IS61LPS25632T-200TQ
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PDF
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Untitled
Abstract: No abstract text available
Text: May 2004 AS7C33512NTF32A AS7C33512NTF36A 3.3V 512K x 32/36 Flowthrough Synchronous SRAM with NTDTM Features • • • • • • • • • • • • • • • • Organization: 524,288 words × 32 or 36 bits NTD 1 architecture for efficient bus operation
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Original
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AS7C33512NTF32A
AS7C33512NTF36A
100-pin
165-ball
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PDF
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Untitled
Abstract: No abstract text available
Text: March 2004 AS7C25512NTD32A AS7C25512NTD36A 2.5V 512K x 32/36 SRAM with NTDTM Features • • • • • • Organization: 524,288 words × 32 or 36 bits NTD 1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/3.8 ns
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AS7C25512NTD32A
AS7C25512NTD36A
100-pin
165-ball
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PDF
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RQW 130
Abstract: No abstract text available
Text: August 2002 Advance Information AS7C33512NTD32A AS7C33512NTD36A 9 . î 65$0 ZLWK 17'TM Features • Organization: 524,288 words x 32 or 36 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 250 MHz in LVTTL/LVCMOS
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Original
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AS7C33512NTD32A
AS7C33512NTD36A
100-pin
165-ball
RQW 130
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PDF
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Untitled
Abstract: No abstract text available
Text: May 2003 Advance Information AS7C33512NTD32A AS7C33512NTD36A 9 . î 65$0 ZLWK 17'TM Features • Organization: 524,288 words x 32 or 36 bits • NTD 1 architecture for efficient bus operation • Fast clock speeds to 200 MHz in LVTTL/LVCMOS
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Original
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AS7C33512NTD32A
AS7C33512NTD36A
100-pin
165-ball
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PDF
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1382C
Abstract: No abstract text available
Text: 380C CY7C1380C CY7C1382C PRELIMINARY 512K x 36 / 1M x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns
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Original
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CY7C1380C
CY7C1382C
119-ball
165-ball
100-pin
CY7C1380C/CY7C1382C
BG119)
BB165A)
1382C
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PDF
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CY7C1381c-100ac
Abstract: No abstract text available
Text: 381C CY7C1381C CY7C1383C PRELIMINARY 512K x 36/1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • • Fast access times: 6.5, 7.5, 8.5 ns Fast clock speed: 133, 117, 100 MHz Provide high-performance 2-1-1-1 access rate Optimal for depth expansion
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Original
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CY7C1381C
CY7C1383C
36/1M
100-pin
119-ball
165-ball
CY7C1381C/CY7C1383C
CY7C1381c-100ac
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PDF
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1382C
Abstract: No abstract text available
Text: CY7C1380C CY7C1382C 512K x 36/1M x 18 Pipelined SRAM Features Functional Description • Fast clock speed: 250, 225, 200, 167, 133 MHz • Provide high-performance 3-1-1-1 access rate • Fast OE access times: 2.6, 2.8, 3.0, 3.4, 4.2ns • Optimal for depth expansion
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Original
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CY7C1380C
CY7C1382C
36/1M
119-ball
165-ball
100-pin
CY7C1380C/CY7C1382C
1382C
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PDF
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CY7C1440V33
Abstract: No abstract text available
Text: CY7C1440V33 CY7C1442V33 CY7C1446V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.7, 3.0 and 3.5 ns
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Original
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CY7C1440V33
CY7C1442V33
CY7C1446V33
36/2M
18/512K
CY7C1440V33/CY7C1442V33/CY7C1446V33
CY7C1440V33
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PDF
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CY7C1370B
Abstract: CY7C1372B
Text: CY7C1370B CY7C1372B 512K x 36/1M × 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 167, 150, and 133 MHz • Fast access time: 3.0, 3.4, 3.8, and 4.2 ns • Internally synchronized registered outputs eliminate
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Original
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CY7C1370B
CY7C1372B
36/1M
CY7C1370B/CY7C1372B
36/1M
CY7C1370B
CY7C1372B
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PDF
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CY7C1371
Abstract: CY7C1371B CY7C1373 CY7C1373B
Text: CY7C1371B CY7C1373B 73B 512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT devices • Supports 117-MHz bus operations with zero wait states — Data is transferred on every clock
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Original
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CY7C1371B
CY7C1373B
36/1M
117-MHz
100-MHz
83-MHz
CY7C1371B/CY7C1373B
CY7C1371
CY7C1371B
CY7C1373
CY7C1373B
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PDF
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Untitled
Abstract: No abstract text available
Text: for spec. confirmation SUN HM67S36130 Series 131072 words x 36 bits Synchronous Fast Static RAM Product Preview Rev. 3 HITACHI Features Pin Arrangement • 3.3V:t 5% Operation • LVCMOS Compatible Input and Output Synchronous Operation Internal self-timed Late Write
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OCR Scan
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HM67S36130
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE M I ir a n M 256K x 18/128K x 36 2.5V I/O, FLOW-THROUGH LATE WRITE SRAM A C|U|h I A T F MT59L256V18F MT59L128V36F 1 •- WRITE SRAM Dual Clock and Single Clock FEATURES • • • • • • • • • • • • • • • • • Fast cycle tim es 4.5ns, 5ns, 6ns and 7ns
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OCR Scan
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18/128K
MT59L256V18F
MT59L128V36F
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE 256K x 18/128K x 36 HSTL, PIPELINED LATE WRITE SRAM MT59L256H18P MT59L128H36P 4.5Mb LATE WRITE SRAM FEATURES • • • • • • • • • • • • • • • • • • Fast cycle times 4.5ns, 5ns, 6ns and 7ns 256K x 18 or 128K x 36 configurations
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OCR Scan
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18/128K
MT59L256H18P
MT59L128H36P
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE M IC F 3 0 N 1 2 5 6 K X 1 8 /1 2 8 K x 36 H S T L , P I P E L IN E D L A T E W R IT E S R A M A C M h I A T F WRITE SRAM FEATURES • Fast cycle tim es 4.5ns, 5ns, 6ns and 7ns • 256K x 18 or 128K x 36 configurations • Single +3.3V + 0 .3 V /-0 .2 V pow er supply (V dd)
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OCR Scan
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MT59L256H18P
MT59L128H36P
18/12BK
MT59L256H1BP
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PDF
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